1 #ifndef CAPSTONE_XCORE_H 2 #define CAPSTONE_XCORE_H 3 4 /* Capstone Disassembly Engine */ 5 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #include "platform.h" 12 13 #ifdef _MSC_VER 14 #pragma warning(disable:4201) 15 #endif 16 17 /// Operand type for instruction's operands 18 typedef enum xcore_op_type { 19 XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 20 XCORE_OP_REG, ///< = CS_OP_REG (Register operand). 21 XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand). 22 XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand). 23 } xcore_op_type; 24 25 /// XCore registers 26 typedef enum xcore_reg { 27 XCORE_REG_INVALID = 0, 28 29 XCORE_REG_CP, 30 XCORE_REG_DP, 31 XCORE_REG_LR, 32 XCORE_REG_SP, 33 XCORE_REG_R0, 34 XCORE_REG_R1, 35 XCORE_REG_R2, 36 XCORE_REG_R3, 37 XCORE_REG_R4, 38 XCORE_REG_R5, 39 XCORE_REG_R6, 40 XCORE_REG_R7, 41 XCORE_REG_R8, 42 XCORE_REG_R9, 43 XCORE_REG_R10, 44 XCORE_REG_R11, 45 46 // pseudo registers 47 XCORE_REG_PC, ///< pc 48 49 // internal thread registers 50 // see The-XMOS-XS1-Architecture(X7879A).pdf 51 XCORE_REG_SCP, ///< save pc 52 XCORE_REG_SSR, //< save status 53 XCORE_REG_ET, //< exception type 54 XCORE_REG_ED, //< exception data 55 XCORE_REG_SED, //< save exception data 56 XCORE_REG_KEP, //< kernel entry pointer 57 XCORE_REG_KSP, //< kernel stack pointer 58 XCORE_REG_ID, //< thread ID 59 60 XCORE_REG_ENDING, // <-- mark the end of the list of registers 61 } xcore_reg; 62 63 /// Instruction's operand referring to memory 64 /// This is associated with XCORE_OP_MEM operand type above 65 typedef struct xcore_op_mem { 66 uint8_t base; ///< base register, can be safely interpreted as 67 ///< a value of type `xcore_reg`, but it is only 68 ///< one byte wide 69 uint8_t index; ///< index register, same conditions apply here 70 int32_t disp; ///< displacement/offset value 71 int direct; ///< +1: forward, -1: backward 72 } xcore_op_mem; 73 74 /// Instruction operand 75 typedef struct cs_xcore_op { 76 xcore_op_type type; ///< operand type 77 union { 78 xcore_reg reg; ///< register value for REG operand 79 int32_t imm; ///< immediate value for IMM operand 80 xcore_op_mem mem; ///< base/disp value for MEM operand 81 }; 82 } cs_xcore_op; 83 84 /// Instruction structure 85 typedef struct cs_xcore { 86 /// Number of operands of this instruction, 87 /// or 0 when instruction has no operand. 88 uint8_t op_count; 89 cs_xcore_op operands[8]; ///< operands for this instruction. 90 } cs_xcore; 91 92 /// XCore instruction 93 typedef enum xcore_insn { 94 XCORE_INS_INVALID = 0, 95 96 XCORE_INS_ADD, 97 XCORE_INS_ANDNOT, 98 XCORE_INS_AND, 99 XCORE_INS_ASHR, 100 XCORE_INS_BAU, 101 XCORE_INS_BITREV, 102 XCORE_INS_BLA, 103 XCORE_INS_BLAT, 104 XCORE_INS_BL, 105 XCORE_INS_BF, 106 XCORE_INS_BT, 107 XCORE_INS_BU, 108 XCORE_INS_BRU, 109 XCORE_INS_BYTEREV, 110 XCORE_INS_CHKCT, 111 XCORE_INS_CLRE, 112 XCORE_INS_CLRPT, 113 XCORE_INS_CLRSR, 114 XCORE_INS_CLZ, 115 XCORE_INS_CRC8, 116 XCORE_INS_CRC32, 117 XCORE_INS_DCALL, 118 XCORE_INS_DENTSP, 119 XCORE_INS_DGETREG, 120 XCORE_INS_DIVS, 121 XCORE_INS_DIVU, 122 XCORE_INS_DRESTSP, 123 XCORE_INS_DRET, 124 XCORE_INS_ECALLF, 125 XCORE_INS_ECALLT, 126 XCORE_INS_EDU, 127 XCORE_INS_EEF, 128 XCORE_INS_EET, 129 XCORE_INS_EEU, 130 XCORE_INS_ENDIN, 131 XCORE_INS_ENTSP, 132 XCORE_INS_EQ, 133 XCORE_INS_EXTDP, 134 XCORE_INS_EXTSP, 135 XCORE_INS_FREER, 136 XCORE_INS_FREET, 137 XCORE_INS_GETD, 138 XCORE_INS_GET, 139 XCORE_INS_GETN, 140 XCORE_INS_GETR, 141 XCORE_INS_GETSR, 142 XCORE_INS_GETST, 143 XCORE_INS_GETTS, 144 XCORE_INS_INCT, 145 XCORE_INS_INIT, 146 XCORE_INS_INPW, 147 XCORE_INS_INSHR, 148 XCORE_INS_INT, 149 XCORE_INS_IN, 150 XCORE_INS_KCALL, 151 XCORE_INS_KENTSP, 152 XCORE_INS_KRESTSP, 153 XCORE_INS_KRET, 154 XCORE_INS_LADD, 155 XCORE_INS_LD16S, 156 XCORE_INS_LD8U, 157 XCORE_INS_LDA16, 158 XCORE_INS_LDAP, 159 XCORE_INS_LDAW, 160 XCORE_INS_LDC, 161 XCORE_INS_LDW, 162 XCORE_INS_LDIVU, 163 XCORE_INS_LMUL, 164 XCORE_INS_LSS, 165 XCORE_INS_LSUB, 166 XCORE_INS_LSU, 167 XCORE_INS_MACCS, 168 XCORE_INS_MACCU, 169 XCORE_INS_MJOIN, 170 XCORE_INS_MKMSK, 171 XCORE_INS_MSYNC, 172 XCORE_INS_MUL, 173 XCORE_INS_NEG, 174 XCORE_INS_NOT, 175 XCORE_INS_OR, 176 XCORE_INS_OUTCT, 177 XCORE_INS_OUTPW, 178 XCORE_INS_OUTSHR, 179 XCORE_INS_OUTT, 180 XCORE_INS_OUT, 181 XCORE_INS_PEEK, 182 XCORE_INS_REMS, 183 XCORE_INS_REMU, 184 XCORE_INS_RETSP, 185 XCORE_INS_SETCLK, 186 XCORE_INS_SET, 187 XCORE_INS_SETC, 188 XCORE_INS_SETD, 189 XCORE_INS_SETEV, 190 XCORE_INS_SETN, 191 XCORE_INS_SETPSC, 192 XCORE_INS_SETPT, 193 XCORE_INS_SETRDY, 194 XCORE_INS_SETSR, 195 XCORE_INS_SETTW, 196 XCORE_INS_SETV, 197 XCORE_INS_SEXT, 198 XCORE_INS_SHL, 199 XCORE_INS_SHR, 200 XCORE_INS_SSYNC, 201 XCORE_INS_ST16, 202 XCORE_INS_ST8, 203 XCORE_INS_STW, 204 XCORE_INS_SUB, 205 XCORE_INS_SYNCR, 206 XCORE_INS_TESTCT, 207 XCORE_INS_TESTLCL, 208 XCORE_INS_TESTWCT, 209 XCORE_INS_TSETMR, 210 XCORE_INS_START, 211 XCORE_INS_WAITEF, 212 XCORE_INS_WAITET, 213 XCORE_INS_WAITEU, 214 XCORE_INS_XOR, 215 XCORE_INS_ZEXT, 216 217 XCORE_INS_ENDING, // <-- mark the end of the list of instructions 218 } xcore_insn; 219 220 /// Group of XCore instructions 221 typedef enum xcore_insn_group { 222 XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID 223 224 // Generic groups 225 // all jump instructions (conditional+direct+indirect jumps) 226 XCORE_GRP_JUMP, ///< = CS_GRP_JUMP 227 228 XCORE_GRP_ENDING, // <-- mark the end of the list of groups 229 } xcore_insn_group; 230 231 #ifdef __cplusplus 232 } 233 #endif 234 235 #endif 236