1//===-- AVX512Ops.td - AVX512 dialect operation definitions *- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the basic operations for the AVX512 dialect. 10// 11//===----------------------------------------------------------------------===// 12 13#ifndef AVX512_OPS 14#define AVX512_OPS 15 16include "mlir/Interfaces/SideEffectInterfaces.td" 17 18//===----------------------------------------------------------------------===// 19// AVX512 dialect definition 20//===----------------------------------------------------------------------===// 21 22def AVX512_Dialect : Dialect { 23 let name = "avx512"; 24 let cppNamespace = "::mlir::avx512"; 25} 26 27//===----------------------------------------------------------------------===// 28// AVX512 op definitions 29//===----------------------------------------------------------------------===// 30 31class AVX512_Op<string mnemonic, list<OpTrait> traits = []> : 32 Op<AVX512_Dialect, mnemonic, traits> {} 33 34def MaskRndScaleOp : AVX512_Op<"mask.rndscale", [NoSideEffect, 35 AllTypesMatch<["src", "a", "dst"]>, 36 TypesMatchWith<"imm has the same number of bits as elements in dst", 37 "dst", "imm", 38 "IntegerType::get(($_self.cast<VectorType>().getShape()[0])," 39 " $_self.getContext())">]> { 40 let summary = "Masked roundscale op"; 41 let description = [{ 42 The mask.rndscale op is an AVX512 specific op that can lower to the proper 43 LLVMAVX512 operation: `llvm.mask.rndscale.ps.512` or 44 `llvm.mask.rndscale.pd.512` instruction depending on the type of vectors it 45 is applied to. 46 47 #### From the Intel Intrinsics Guide: 48 49 Round packed floating-point elements in `a` to the number of fraction bits 50 specified by `imm`, and store the results in `dst` using writemask `k` 51 (elements are copied from src when the corresponding mask bit is not set). 52 }]; 53 // Supports vector<16xf32> and vector<8xf64>. 54 let arguments = (ins VectorOfLengthAndType<[16, 8], [F32, F64]>:$src, 55 I32:$k, 56 VectorOfLengthAndType<[16, 8], [F32, F64]>:$a, 57 AnyTypeOf<[I16, I8]>:$imm, 58 // TODO: figure rounding out (optional operand?). 59 I32:$rounding 60 ); 61 let results = (outs VectorOfLengthAndType<[16, 8], [F32, F64]>:$dst); 62 let assemblyFormat = 63 "$src `,` $k `,` $a `,` $imm `,` $rounding attr-dict `:` type($dst)"; 64} 65 66def MaskScaleFOp : AVX512_Op<"mask.scalef", [NoSideEffect, 67 AllTypesMatch<["src", "a", "b", "dst"]>, 68 TypesMatchWith<"k has the same number of bits as elements in dst", 69 "dst", "k", 70 "IntegerType::get(($_self.cast<VectorType>().getShape()[0])," 71 " $_self.getContext())">]> { 72 let summary = "ScaleF op"; 73 let description = [{ 74 The `mask.scalef` op is an AVX512 specific op that can lower to the proper 75 LLVMAVX512 operation: `llvm.mask.scalef.ps.512` or 76 `llvm.mask.scalef.pd.512` depending on the type of MLIR vectors it is 77 applied to. 78 79 #### From the Intel Intrinsics Guide: 80 81 Scale the packed floating-point elements in `a` using values from `b`, and 82 store the results in `dst` using writemask `k` (elements are copied from src 83 when the corresponding mask bit is not set). 84 }]; 85 // Supports vector<16xf32> and vector<8xf64>. 86 let arguments = (ins VectorOfLengthAndType<[16, 8], [F32, F64]>:$src, 87 VectorOfLengthAndType<[16, 8], [F32, F64]>:$a, 88 VectorOfLengthAndType<[16, 8], [F32, F64]>:$b, 89 AnyTypeOf<[I16, I8]>:$k, 90 // TODO: figure rounding out (optional operand?). 91 I32:$rounding 92 ); 93 let results = (outs VectorOfLengthAndType<[16, 8], [F32, F64]>:$dst); 94 // Fully specified by traits. 95 let assemblyFormat = 96 "$src `,` $a `,` $b `,` $k `,` $rounding attr-dict `:` type($dst)"; 97} 98 99#endif // AVX512_OPS 100