1//===- StandardOpsBase.td - Standard ops definitions -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Defines base support for standard operations.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef STANDARD_OPS_BASE
14#define STANDARD_OPS_BASE
15
16include "mlir/IR/OpBase.td"
17
18def ATOMIC_RMW_KIND_ADDF    : I64EnumAttrCase<"addf", 0>;
19def ATOMIC_RMW_KIND_ADDI    : I64EnumAttrCase<"addi", 1>;
20def ATOMIC_RMW_KIND_ASSIGN  : I64EnumAttrCase<"assign", 2>;
21def ATOMIC_RMW_KIND_MAXF    : I64EnumAttrCase<"maxf", 3>;
22def ATOMIC_RMW_KIND_MAXS    : I64EnumAttrCase<"maxs", 4>;
23def ATOMIC_RMW_KIND_MAXU    : I64EnumAttrCase<"maxu", 5>;
24def ATOMIC_RMW_KIND_MINF    : I64EnumAttrCase<"minf", 6>;
25def ATOMIC_RMW_KIND_MINS    : I64EnumAttrCase<"mins", 7>;
26def ATOMIC_RMW_KIND_MINU    : I64EnumAttrCase<"minu", 8>;
27def ATOMIC_RMW_KIND_MULF    : I64EnumAttrCase<"mulf", 9>;
28def ATOMIC_RMW_KIND_MULI    : I64EnumAttrCase<"muli", 10>;
29
30def AtomicRMWKindAttr : I64EnumAttr<
31    "AtomicRMWKind", "",
32    [ATOMIC_RMW_KIND_ADDF, ATOMIC_RMW_KIND_ADDI, ATOMIC_RMW_KIND_ASSIGN,
33     ATOMIC_RMW_KIND_MAXF, ATOMIC_RMW_KIND_MAXS, ATOMIC_RMW_KIND_MAXU,
34     ATOMIC_RMW_KIND_MINF, ATOMIC_RMW_KIND_MINS, ATOMIC_RMW_KIND_MINU,
35     ATOMIC_RMW_KIND_MULF, ATOMIC_RMW_KIND_MULI]> {
36  let cppNamespace = "::mlir";
37}
38
39#endif // STANDARD_OPS_BASE
40