1 /* 2 * Copyright � 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #ifndef _INTEL_BIOS_H_ 29 #define _INTEL_BIOS_H_ 30 31 #include <stdint.h> 32 33 #define DEVICE_HANDLE_CRT 0x01 34 #define DEVICE_HANDLE_EFP1 0x04 35 #define DEVICE_HANDLE_EFP2 0x40 36 #define DEVICE_HANDLE_EFP3 0x20 37 #define DEVICE_HANDLE_EFP4 0x10 38 #define DEVICE_HANDLE_LPF1 0x08 39 #define DEVICE_HANDLE_LFP2 0x80 40 41 #define DEVICE_TYPE_DP_DVI 0x68d6 42 #define DEVICE_TYPE_DVI 0x68d2 43 #define DEVICE_TYPE_MIPI 0x7cc2 44 45 struct bdb_legacy_child_devices { 46 uint8_t child_dev_size; 47 uint8_t devices[0]; /* presumably 7 * 33 */ 48 } __attribute__ ((packed)); 49 50 #define BDB_DRIVER_NO_LVDS 0 51 #define BDB_DRIVER_INT_LVDS 1 52 #define BDB_DRIVER_SDVO_LVDS 2 53 #define BDB_DRIVER_EDP 3 54 55 struct edp_power_seq { 56 uint16_t t3; 57 uint16_t t7; 58 uint16_t t9; 59 uint16_t t10; 60 uint16_t t12; 61 } __attribute__ ((packed)); 62 63 /* Block 52 contains MiPi Panel info 64 * 6 such enteries will there. Index into correct 65 * entery is based on the panel_index in #40 LFP 66 */ 67 #define MAX_MIPI_CONFIGURATIONS 6 68 struct mipi_config { 69 uint16_t panel_id; 70 71 /* General Params */ 72 uint32_t dithering:1; 73 uint32_t rsvd1:1; 74 uint32_t panel_type:1; 75 uint32_t panel_arch_type:2; 76 uint32_t cmd_mode:1; 77 uint32_t vtm:2; 78 uint32_t cabc:1; 79 uint32_t pwm_blc:1; 80 81 /* Bit 13:10 82 * 000 - Reserved, 001 - RGB565, 002 - RGB666, 83 * 011 - RGB666Loosely packed, 100 - RGB888, 84 * others - rsvd 85 */ 86 uint32_t videomode_color_format:4; 87 88 /* Bit 15:14 89 * 0 - No rotation, 1 - 90 degree 90 * 2 - 180 degree, 3 - 270 degree 91 */ 92 uint32_t rotation:2; 93 uint32_t bta:1; 94 uint32_t rsvd2:15; 95 96 /* 2 byte Port Description */ 97 uint16_t dual_link:2; 98 uint16_t lane_cnt:2; 99 uint16_t pixel_overlap:3; 100 uint16_t rsvd3:9; 101 102 /* 2 byte DSI COntroller params */ 103 /* 0 - Using DSI PHY, 1 - TE usage */ 104 uint16_t dsi_usage:1; 105 uint16_t rsvd4:15; 106 107 uint8_t rsvd5[5]; 108 uint32_t dsi_ddr_clk; 109 uint32_t bridge_ref_clk; 110 111 uint8_t byte_clk_sel:2; 112 uint8_t rsvd6:6; 113 114 /* DPHY Flags */ 115 uint16_t dphy_param_valid:1; 116 uint16_t eot_disabled:1; 117 uint16_t clk_stop:1; 118 uint16_t rsvd7:13; 119 120 uint32_t hs_tx_timeout; 121 uint32_t lp_rx_timeout; 122 uint32_t turn_around_timeout; 123 uint32_t device_reset_timer; 124 uint32_t master_init_timer; 125 uint32_t dbi_bw_timer; 126 uint32_t lp_byte_clk_val; 127 128 /* 4 byte Dphy Params */ 129 uint32_t prepare_cnt:6; 130 uint32_t rsvd8:2; 131 uint32_t clk_zero_cnt:8; 132 uint32_t trail_cnt:5; 133 uint32_t rsvd9:3; 134 uint32_t exit_zero_cnt:6; 135 uint32_t rsvd10:2; 136 137 uint32_t clk_lane_switch_cnt; 138 uint32_t hl_switch_cnt; 139 140 uint32_t rsvd11[6]; 141 142 /* timings based on dphy spec */ 143 uint8_t tclk_miss; 144 uint8_t tclk_post; 145 uint8_t rsvd12; 146 uint8_t tclk_pre; 147 uint8_t tclk_prepare; 148 uint8_t tclk_settle; 149 uint8_t tclk_term_enable; 150 uint8_t tclk_trail; 151 uint16_t tclk_prepare_clkzero; 152 uint8_t rsvd13; 153 uint8_t td_term_enable; 154 uint8_t teot; 155 uint8_t ths_exit; 156 uint8_t ths_prepare; 157 uint16_t ths_prepare_hszero; 158 uint8_t rsvd14; 159 uint8_t ths_settle; 160 uint8_t ths_skip; 161 uint8_t ths_trail; 162 uint8_t tinit; 163 uint8_t tlpx; 164 uint8_t rsvd15[3]; 165 166 /* GPIOs */ 167 uint8_t panel_enable; 168 uint8_t bl_enable; 169 uint8_t pwm_enable; 170 uint8_t reset_r_n; 171 uint8_t pwr_down_r; 172 uint8_t stdby_r_n; 173 174 } __attribute__ ((packed)); 175 176 /* Block 52 contains MiPi configuration block 177 * 6 * bdb_mipi_config, followed by 6 pps data 178 * block below 179 */ 180 struct mipi_pps_data { 181 uint16_t panel_on_delay; 182 uint16_t bl_enable_delay; 183 uint16_t bl_disable_delay; 184 uint16_t panel_off_delay; 185 uint16_t panel_power_cycle_delay; 186 } __attribute__ ((packed)); 187 188 /* MIPI Sequence Block definitions */ 189 enum mipi_seq { 190 MIPI_SEQ_END = 0, 191 MIPI_SEQ_ASSERT_RESET, 192 MIPI_SEQ_INIT_OTP, 193 MIPI_SEQ_DISPLAY_ON, 194 MIPI_SEQ_DISPLAY_OFF, 195 MIPI_SEQ_DEASSERT_RESET, 196 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 197 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 198 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 199 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 200 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 201 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 202 MIPI_SEQ_MAX 203 }; 204 205 enum mipi_seq_element { 206 MIPI_SEQ_ELEM_END = 0, 207 MIPI_SEQ_ELEM_SEND_PKT, 208 MIPI_SEQ_ELEM_DELAY, 209 MIPI_SEQ_ELEM_GPIO, 210 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 211 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 212 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 213 MIPI_SEQ_ELEM_MAX 214 }; 215 216 #endif /* _INTEL_BIOS_H_ */ 217