1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Mika Kuoppala <mika.kuoppala@intel.com>
25 */
26
27 #include "intel_renderstate.h"
28 #include <lib/gen7_render.h>
29 #include <lib/intel_reg.h>
30 #include <string.h>
31
32 static const uint32_t ps_kernel[][4] = {
33 { 0x0080005a, 0x2e2077bd, 0x000000c0, 0x008d0040 },
34 { 0x0080005a, 0x2e6077bd, 0x000000d0, 0x008d0040 },
35 { 0x02800031, 0x21801fa9, 0x008d0e20, 0x08840001 },
36 { 0x00800001, 0x2e2003bd, 0x008d0180, 0x00000000 },
37 { 0x00800001, 0x2e6003bd, 0x008d01c0, 0x00000000 },
38 { 0x00800001, 0x2ea003bd, 0x008d0200, 0x00000000 },
39 { 0x00800001, 0x2ee003bd, 0x008d0240, 0x00000000 },
40 { 0x05800031, 0x20001fa8, 0x008d0e20, 0x90031000 },
41 };
42
43 static uint32_t
gen7_bind_buf_null(struct intel_batchbuffer * batch)44 gen7_bind_buf_null(struct intel_batchbuffer *batch)
45 {
46 return intel_batch_state_alloc(batch, 32, 32, "bind buf null");
47 }
48
49 static void
gen7_emit_vertex_elements(struct intel_batchbuffer * batch)50 gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
51 {
52 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
53 ((2 * (1 + 2)) + 1 - 2));
54
55 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
56 SURFACEFORMAT_R32G32B32A32_FLOAT <<
57 VE0_FORMAT_SHIFT |
58 0 << VE0_OFFSET_SHIFT);
59
60 OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
61 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
62 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
63 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
64
65 /* x,y */
66 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
67 SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
68 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
69 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
70 GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
71 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
72 GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
73
74 /* s,t */
75 OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
76 SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
77 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
78 OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
79 GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
80 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
81 GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
82 }
83
84 static uint32_t
gen7_create_vertex_buffer(struct intel_batchbuffer * batch)85 gen7_create_vertex_buffer(struct intel_batchbuffer *batch)
86 {
87 uint16_t *v;
88
89 return intel_batch_state_alloc(batch, 12*sizeof(*v), 8, "vertex buffer");
90 }
91
gen7_emit_vertex_buffer(struct intel_batchbuffer * batch)92 static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch)
93 {
94 uint32_t offset;
95
96 offset = gen7_create_vertex_buffer(batch);
97
98 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2));
99 OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
100 GEN6_VB0_VERTEXDATA |
101 GEN7_VB0_ADDRESS_MODIFY_ENABLE |
102 VB0_NULL_VERTEX_BUFFER |
103 4*2 << VB0_BUFFER_PITCH_SHIFT);
104
105 OUT_RELOC_STATE(batch, I915_GEM_DOMAIN_VERTEX, 0, offset);
106 OUT_BATCH(~0);
107 OUT_BATCH(0);
108 }
109
110 static uint32_t
gen7_bind_surfaces(struct intel_batchbuffer * batch)111 gen7_bind_surfaces(struct intel_batchbuffer *batch)
112 {
113 unsigned offset;
114
115 offset = intel_batch_state_alloc(batch, 8, 32, "bind surfaces");
116
117 bb_area_emit_offset(batch->state, offset, gen7_bind_buf_null(batch), STATE_OFFSET, "bind 1");
118 bb_area_emit_offset(batch->state, offset + 4, gen7_bind_buf_null(batch), STATE_OFFSET, "bind 2");
119
120 return offset;
121 }
122
123 static void
gen7_emit_binding_table(struct intel_batchbuffer * batch)124 gen7_emit_binding_table(struct intel_batchbuffer *batch)
125 {
126 OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
127 OUT_BATCH_STATE_OFFSET(gen7_bind_surfaces(batch));
128 }
129
130 static void
gen7_emit_drawing_rectangle(struct intel_batchbuffer * batch)131 gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch)
132 {
133 OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
134 /* Purposedly set min > max for null rectangle */
135 OUT_BATCH(0xffffffff);
136 OUT_BATCH(0 | 0);
137 OUT_BATCH(0);
138 }
139
140 static uint32_t
gen7_create_blend_state(struct intel_batchbuffer * batch)141 gen7_create_blend_state(struct intel_batchbuffer *batch)
142 {
143 struct gen6_blend_state blend;
144 memset(&blend, 0, sizeof(blend));
145
146 blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
147 blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
148 blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
149 blend.blend1.post_blend_clamp_enable = 1;
150 blend.blend1.pre_blend_clamp_enable = 1;
151
152 return OUT_STATE_STRUCT(blend, 64);
153 }
154
155 static void
gen7_emit_state_base_address(struct intel_batchbuffer * batch)156 gen7_emit_state_base_address(struct intel_batchbuffer *batch)
157 {
158 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
159 OUT_BATCH(0);
160 OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
161 OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
162 OUT_BATCH(0);
163 OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
164
165 OUT_BATCH(0);
166 OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
167 OUT_BATCH(0);
168 OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
169 }
170
171 static uint32_t
gen7_create_cc_viewport(struct intel_batchbuffer * batch)172 gen7_create_cc_viewport(struct intel_batchbuffer *batch)
173 {
174 struct gen4_cc_viewport vp;
175 memset(&vp, 0, sizeof(vp));
176
177 vp.min_depth = -1.e35;
178 vp.max_depth = 1.e35;
179
180 return OUT_STATE_STRUCT(vp, 32);
181 }
182
183 static void
gen7_emit_cc(struct intel_batchbuffer * batch)184 gen7_emit_cc(struct intel_batchbuffer *batch)
185 {
186 OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
187 OUT_BATCH_STATE_OFFSET(gen7_create_blend_state(batch));
188
189 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
190 OUT_BATCH_STATE_OFFSET(gen7_create_cc_viewport(batch));
191 }
192
193 static uint32_t
gen7_create_sampler(struct intel_batchbuffer * batch)194 gen7_create_sampler(struct intel_batchbuffer *batch)
195 {
196 struct gen7_sampler_state ss;
197 memset(&ss, 0, sizeof(ss));
198
199 ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST;
200 ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
201
202 ss.ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
203 ss.ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
204 ss.ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
205
206 ss.ss3.non_normalized_coord = 1;
207
208 return OUT_STATE_STRUCT(ss, 32);
209 }
210
211 static void
gen7_emit_sampler(struct intel_batchbuffer * batch)212 gen7_emit_sampler(struct intel_batchbuffer *batch)
213 {
214 OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
215 OUT_BATCH_STATE_OFFSET(gen7_create_sampler(batch));
216 }
217
218 static void
gen7_emit_multisample(struct intel_batchbuffer * batch)219 gen7_emit_multisample(struct intel_batchbuffer *batch)
220 {
221 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
222 OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
223 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
224 OUT_BATCH(0);
225 OUT_BATCH(0);
226
227 OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
228 OUT_BATCH(1);
229 }
230
231 static void
gen7_emit_urb(struct intel_batchbuffer * batch)232 gen7_emit_urb(struct intel_batchbuffer *batch)
233 {
234 OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
235 OUT_BATCH(8); /* in 1KBs */
236
237 /* num of VS entries must be divisible by 8 if size < 9 */
238 OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
239 OUT_BATCH((64 << GEN7_URB_ENTRY_NUMBER_SHIFT) |
240 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
241 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
242
243 OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
244 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
245 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
246
247 OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
248 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
249 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
250
251 OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
252 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
253 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
254 }
255
256 static void
gen7_emit_vs(struct intel_batchbuffer * batch)257 gen7_emit_vs(struct intel_batchbuffer *batch)
258 {
259 OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
260 OUT_BATCH(0); /* no VS kernel */
261 OUT_BATCH(0);
262 OUT_BATCH(0);
263 OUT_BATCH(0);
264 OUT_BATCH(0); /* pass-through */
265 }
266
267 static void
gen7_emit_hs(struct intel_batchbuffer * batch)268 gen7_emit_hs(struct intel_batchbuffer *batch)
269 {
270 OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
271 OUT_BATCH(0); /* no HS kernel */
272 OUT_BATCH(0);
273 OUT_BATCH(0);
274 OUT_BATCH(0);
275 OUT_BATCH(0);
276 OUT_BATCH(0); /* pass-through */
277 }
278
279 static void
gen7_emit_te(struct intel_batchbuffer * batch)280 gen7_emit_te(struct intel_batchbuffer *batch)
281 {
282 OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
283 OUT_BATCH(0);
284 OUT_BATCH(0);
285 OUT_BATCH(0);
286 }
287
288 static void
gen7_emit_ds(struct intel_batchbuffer * batch)289 gen7_emit_ds(struct intel_batchbuffer *batch)
290 {
291 OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
292 OUT_BATCH(0);
293 OUT_BATCH(0);
294 OUT_BATCH(0);
295 OUT_BATCH(0);
296 OUT_BATCH(0);
297 }
298
299 static void
gen7_emit_gs(struct intel_batchbuffer * batch)300 gen7_emit_gs(struct intel_batchbuffer *batch)
301 {
302 OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
303 OUT_BATCH(0); /* no GS kernel */
304 OUT_BATCH(0);
305 OUT_BATCH(0);
306 OUT_BATCH(0);
307 OUT_BATCH(0);
308 OUT_BATCH(0); /* pass-through */
309 }
310
311 static void
gen7_emit_streamout(struct intel_batchbuffer * batch)312 gen7_emit_streamout(struct intel_batchbuffer *batch)
313 {
314 OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
315 OUT_BATCH(0);
316 OUT_BATCH(0);
317 }
318
319 static void
gen7_emit_sf(struct intel_batchbuffer * batch)320 gen7_emit_sf(struct intel_batchbuffer *batch)
321 {
322 OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
323 OUT_BATCH(0);
324 OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
325 OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
326 OUT_BATCH(0);
327 OUT_BATCH(0);
328 OUT_BATCH(0);
329 }
330
331 static void
gen7_emit_sbe(struct intel_batchbuffer * batch)332 gen7_emit_sbe(struct intel_batchbuffer *batch)
333 {
334 OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
335 OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
336 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
337 1 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
338 OUT_BATCH(0);
339 OUT_BATCH(0); /* dw4 */
340 OUT_BATCH(0);
341 OUT_BATCH(0);
342 OUT_BATCH(0);
343 OUT_BATCH(0); /* dw8 */
344 OUT_BATCH(0);
345 OUT_BATCH(0);
346 OUT_BATCH(0);
347 OUT_BATCH(0); /* dw12 */
348 OUT_BATCH(0);
349 OUT_BATCH(0);
350 }
351
352 static void
gen7_emit_ps(struct intel_batchbuffer * batch)353 gen7_emit_ps(struct intel_batchbuffer *batch)
354 {
355 int threads;
356
357 #if 0 /* XXX: Do we need separate state for hsw or not */
358 if (IS_HASWELL(batch->dev))
359 threads = 40 << HSW_PS_MAX_THREADS_SHIFT |
360 1 << HSW_PS_SAMPLE_MASK_SHIFT;
361 else
362 #endif
363 threads = 40 << IVB_PS_MAX_THREADS_SHIFT;
364
365 OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
366 OUT_BATCH_STATE_OFFSET(intel_batch_state_copy(batch, ps_kernel,
367 sizeof(ps_kernel), 64, "ps kernel"));
368 OUT_BATCH(1 << GEN7_PS_SAMPLER_COUNT_SHIFT |
369 2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
370 OUT_BATCH(0); /* scratch address */
371 OUT_BATCH(threads |
372 GEN7_PS_16_DISPATCH_ENABLE |
373 GEN7_PS_ATTRIBUTE_ENABLE);
374 OUT_BATCH(6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
375 OUT_BATCH(0);
376 OUT_BATCH(0);
377 }
378
379 static void
gen7_emit_clip(struct intel_batchbuffer * batch)380 gen7_emit_clip(struct intel_batchbuffer *batch)
381 {
382 OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
383 OUT_BATCH(0);
384 OUT_BATCH(0); /* pass-through */
385 OUT_BATCH(0);
386
387 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
388 OUT_BATCH(0);
389 }
390
391 static void
gen7_emit_wm(struct intel_batchbuffer * batch)392 gen7_emit_wm(struct intel_batchbuffer *batch)
393 {
394 OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
395 OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
396 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
397 OUT_BATCH(0);
398 }
399
400 static void
gen7_emit_null_depth_buffer(struct intel_batchbuffer * batch)401 gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
402 {
403 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
404 OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
405 GEN4_DEPTHFORMAT_D32_FLOAT <<
406 GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
407 OUT_BATCH(0); /* disable depth, stencil and hiz */
408 OUT_BATCH(0);
409 OUT_BATCH(0);
410 OUT_BATCH(0);
411 OUT_BATCH(0);
412
413 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
414 OUT_BATCH(0);
415 OUT_BATCH(0);
416 }
417
gen7_setup_null_render_state(struct intel_batchbuffer * batch)418 void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
419 {
420 OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
421
422 gen7_emit_state_base_address(batch);
423 gen7_emit_multisample(batch);
424 gen7_emit_urb(batch);
425 gen7_emit_vs(batch);
426 gen7_emit_hs(batch);
427 gen7_emit_te(batch);
428 gen7_emit_ds(batch);
429 gen7_emit_gs(batch);
430 gen7_emit_clip(batch);
431 gen7_emit_sf(batch);
432 gen7_emit_wm(batch);
433 gen7_emit_streamout(batch);
434 gen7_emit_null_depth_buffer(batch);
435
436 gen7_emit_cc(batch);
437 gen7_emit_sampler(batch);
438 gen7_emit_sbe(batch);
439 gen7_emit_ps(batch);
440 gen7_emit_vertex_elements(batch);
441 gen7_emit_vertex_buffer(batch);
442 gen7_emit_binding_table(batch);
443 gen7_emit_drawing_rectangle(batch);
444
445 OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
446 OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
447 OUT_BATCH(3);
448 OUT_BATCH(0);
449 OUT_BATCH(1); /* single instance */
450 OUT_BATCH(0); /* start instance location */
451 OUT_BATCH(0); /* index buffer offset, ignored */
452
453 OUT_BATCH(MI_BATCH_BUFFER_END);
454 }
455