1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
2;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
3;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
4;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
5
6;GCN-LABEL: {{^}}main:
7;GCN-NOT: s_wqm
8;GCN: s_mov_b32
9;GCN-NEXT: v_interp_mov_f32
10;GCN: v_interp_p1_f32
11;GCN: v_interp_p2_f32
12
13define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) {
14main_body:
15  %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
16  %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
17  %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
18  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
19  ret void
20}
21
22; Thest that v_interp_p1 uses different source and destination registers
23; on 16 bank LDS chips.
24
25; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
26; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
27
28define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
29main_body:
30  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
31  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
32  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
33  %25 = call float @fabs(float %22)
34  %26 = call float @fabs(float %23)
35  %27 = call float @fabs(float %24)
36  %28 = call i32 @llvm.SI.packf16(float %25, float %26)
37  %29 = bitcast i32 %28 to float
38  %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
39  %31 = bitcast i32 %30 to float
40  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
41  ret void
42}
43
44; Function Attrs: readnone
45declare float @fabs(float) #1
46
47; Function Attrs: nounwind readnone
48declare i32 @llvm.SI.packf16(float, float) #0
49
50; Function Attrs: nounwind readnone
51declare float @llvm.SI.fs.constant(i32, i32, i32) #0
52
53; Function Attrs: nounwind readnone
54declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #0
55
56declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
57
58attributes #0 = { nounwind readnone }
59attributes #1 = { readnone }
60