1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
4
5define i32 @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) {
6; GCN-LABEL: global_atomic_csub:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
10; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
11; GCN-NEXT:    s_waitcnt vmcnt(0)
12; GCN-NEXT:    s_setpc_b64 s[30:31]
13  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
14  ret i32 %ret
15}
16
17define i32 @global_atomic_csub_offset(i32 addrspace(1)* %ptr, i32 %data) {
18; GCN-LABEL: global_atomic_csub_offset:
19; GCN:       ; %bb.0:
20; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
22; GCN-NEXT:    s_movk_i32 s4, 0x1000
23; GCN-NEXT:    s_mov_b32 s5, 0
24; GCN-NEXT:    v_mov_b32_e32 v3, s4
25; GCN-NEXT:    v_mov_b32_e32 v4, s5
26; GCN-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v3
27; GCN-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
28; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
29; GCN-NEXT:    s_waitcnt vmcnt(0)
30; GCN-NEXT:    s_setpc_b64 s[30:31]
31  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
32  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
33  ret i32 %ret
34}
35
36define void @global_atomic_csub_nortn(i32 addrspace(1)* %ptr, i32 %data) {
37; GCN-LABEL: global_atomic_csub_nortn:
38; GCN:       ; %bb.0:
39; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
40; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
41; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
42; GCN-NEXT:    s_waitcnt vmcnt(0)
43; GCN-NEXT:    s_setpc_b64 s[30:31]
44  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
45  ret void
46}
47
48define void @global_atomic_csub_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
49; GCN-LABEL: global_atomic_csub_offset_nortn:
50; GCN:       ; %bb.0:
51; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
52; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
53; GCN-NEXT:    s_movk_i32 s4, 0x1000
54; GCN-NEXT:    s_mov_b32 s5, 0
55; GCN-NEXT:    v_mov_b32_e32 v3, s4
56; GCN-NEXT:    v_mov_b32_e32 v4, s5
57; GCN-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v3
58; GCN-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
59; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
60; GCN-NEXT:    s_waitcnt vmcnt(0)
61; GCN-NEXT:    s_setpc_b64 s[30:31]
62  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
63  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
64  ret void
65}
66
67define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset(i32 addrspace(1)* %ptr, i32 %data) {
68; GCN-LABEL: global_atomic_csub_sgpr_base_offset:
69; GCN:       ; %bb.0:
70; GCN-NEXT:    s_clause 0x1
71; GCN-NEXT:    s_load_dword s2, s[4:5], 0x8
72; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
73; GCN-NEXT:    v_mov_b32_e32 v1, 0x1000
74; GCN-NEXT:    s_waitcnt lgkmcnt(0)
75; GCN-NEXT:    v_mov_b32_e32 v0, s2
76; GCN-NEXT:    global_atomic_csub v0, v1, v0, s[0:1] glc
77; GCN-NEXT:    s_waitcnt vmcnt(0)
78; GCN-NEXT:    global_store_dword v[0:1], v0, off
79; GCN-NEXT:    s_endpgm
80  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
81  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
82  store i32 %ret, i32 addrspace(1)* undef
83  ret void
84}
85
86define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
87; GCN-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
88; GCN:       ; %bb.0:
89; GCN-NEXT:    s_clause 0x1
90; GCN-NEXT:    s_load_dword s2, s[4:5], 0x8
91; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
92; GCN-NEXT:    v_mov_b32_e32 v1, 0x1000
93; GCN-NEXT:    s_waitcnt lgkmcnt(0)
94; GCN-NEXT:    v_mov_b32_e32 v0, s2
95; GCN-NEXT:    global_atomic_csub v0, v1, v0, s[0:1] glc
96; GCN-NEXT:    s_endpgm
97  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
98  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
99  ret void
100}
101
102declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1
103
104attributes #0 = { nounwind willreturn }
105attributes #1 = { argmemonly nounwind }
106