1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-32BANK %s 3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-32BANK %s 4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-16BANK %s 5 6define amdgpu_ps float @interp_f16(float %i, i32 inreg %m0) #0 { 7; GFX9-32BANK-LABEL: interp_f16: 8; GFX9-32BANK: ; %bb.0: 9; GFX9-32BANK-NEXT: s_mov_b32 m0, s0 10; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 11; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y 12; GFX9-32BANK-NEXT: ; return to shader part epilog 13; 14; GFX8-32BANK-LABEL: interp_f16: 15; GFX8-32BANK: ; %bb.0: 16; GFX8-32BANK-NEXT: s_mov_b32 m0, s0 17; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 18; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y 19; GFX8-32BANK-NEXT: ; return to shader part epilog 20; 21; GFX8-16BANK-LABEL: interp_f16: 22; GFX8-16BANK: ; %bb.0: 23; GFX8-16BANK-NEXT: s_mov_b32 m0, s0 24; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y 25; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 26; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 27; GFX8-16BANK-NEXT: ; return to shader part epilog 28 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0) 29 ret float %res 30} 31 32define amdgpu_ps float @interp_f16_high(float %i, i32 inreg %m0) #0 { 33; GFX9-32BANK-LABEL: interp_f16_high: 34; GFX9-32BANK: ; %bb.0: 35; GFX9-32BANK-NEXT: s_mov_b32 m0, s0 36; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 37; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high 38; GFX9-32BANK-NEXT: ; return to shader part epilog 39; 40; GFX8-32BANK-LABEL: interp_f16_high: 41; GFX8-32BANK: ; %bb.0: 42; GFX8-32BANK-NEXT: s_mov_b32 m0, s0 43; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 44; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high 45; GFX8-32BANK-NEXT: ; return to shader part epilog 46; 47; GFX8-16BANK-LABEL: interp_f16_high: 48; GFX8-16BANK: ; %bb.0: 49; GFX8-16BANK-NEXT: s_mov_b32 m0, s0 50; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y 51; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 52; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 high 53; GFX8-16BANK-NEXT: ; return to shader part epilog 54 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 true, i32 %m0) 55 ret float %res 56} 57 58define amdgpu_ps float @interp_f16_0_0(float %i, i32 inreg %m0) #0 { 59; GFX9-32BANK-LABEL: interp_f16_0_0: 60; GFX9-32BANK: ; %bb.0: 61; GFX9-32BANK-NEXT: s_mov_b32 m0, s0 62; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 63; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x 64; GFX9-32BANK-NEXT: ; return to shader part epilog 65; 66; GFX8-32BANK-LABEL: interp_f16_0_0: 67; GFX8-32BANK: ; %bb.0: 68; GFX8-32BANK-NEXT: s_mov_b32 m0, s0 69; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 70; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x 71; GFX8-32BANK-NEXT: ; return to shader part epilog 72; 73; GFX8-16BANK-LABEL: interp_f16_0_0: 74; GFX8-16BANK: ; %bb.0: 75; GFX8-16BANK-NEXT: s_mov_b32 m0, s0 76; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr0.x 77; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 78; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr0.x, v1 79; GFX8-16BANK-NEXT: ; return to shader part epilog 80 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 0, i32 0, i1 false, i32 %m0) 81 ret float %res 82} 83 84; Copy needed to legalize %i 85define amdgpu_ps float @interp_f16_sgpr_i(float inreg %i,i32 inreg %m0) #0 { 86; GFX9-32BANK-LABEL: interp_f16_sgpr_i: 87; GFX9-32BANK: ; %bb.0: 88; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0 89; GFX9-32BANK-NEXT: s_mov_b32 m0, s1 90; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 91; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y 92; GFX9-32BANK-NEXT: ; return to shader part epilog 93; 94; GFX8-32BANK-LABEL: interp_f16_sgpr_i: 95; GFX8-32BANK: ; %bb.0: 96; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0 97; GFX8-32BANK-NEXT: s_mov_b32 m0, s1 98; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 99; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y 100; GFX8-32BANK-NEXT: ; return to shader part epilog 101; 102; GFX8-16BANK-LABEL: interp_f16_sgpr_i: 103; GFX8-16BANK: ; %bb.0: 104; GFX8-16BANK-NEXT: s_mov_b32 m0, s1 105; GFX8-16BANK-NEXT: v_mov_b32_e32 v0, s0 106; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y 107; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 108; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 109; GFX8-16BANK-NEXT: ; return to shader part epilog 110 %res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0) 111 ret float %res 112} 113 114declare float @llvm.amdgcn.interp.p1.f16(float, i32 immarg, i32 immarg, i1 immarg, i32) #0 115 116attributes #0 = { nounwind readnone speculatable } 117