1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 * Copyright (C) 2019-2020 Collabora, Ltd.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include <stdio.h>
29 #include <stdint.h>
30 #include <stdlib.h>
31 #include <assert.h>
32 #include <inttypes.h>
33 #include <ctype.h>
34 #include <string.h>
35 #include "midgard.h"
36 #include "midgard_ops.h"
37 #include "midgard_quirks.h"
38 #include "disassemble.h"
39 #include "helpers.h"
40 #include "util/bitscan.h"
41 #include "util/half_float.h"
42 #include "util/u_math.h"
43
44 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
45
46 static unsigned *midg_tags;
47 static bool is_instruction_int = false;
48
49 /* Stats */
50
51 static struct midgard_disasm_stats midg_stats;
52
53 /* Transform an expanded writemask (duplicated 8-bit format) into its condensed
54 * form (one bit per component) */
55
56 static inline unsigned
condense_writemask(unsigned expanded_mask,unsigned bits_per_component)57 condense_writemask(unsigned expanded_mask,
58 unsigned bits_per_component)
59 {
60 if (bits_per_component == 8) {
61 /* Duplicate every bit to go from 8 to 16-channel wrmask */
62 unsigned omask = 0;
63
64 for (unsigned i = 0; i < 8; ++i) {
65 if (expanded_mask & (1 << i))
66 omask |= (3 << (2 * i));
67 }
68
69 return omask;
70 }
71
72 unsigned slots_per_component = bits_per_component / 16;
73 unsigned max_comp = (16 * 8) / bits_per_component;
74 unsigned condensed_mask = 0;
75
76 for (unsigned i = 0; i < max_comp; i++) {
77 if (expanded_mask & (1 << (i * slots_per_component)))
78 condensed_mask |= (1 << i);
79 }
80
81 return condensed_mask;
82 }
83
84 static void
print_alu_opcode(FILE * fp,midgard_alu_op op)85 print_alu_opcode(FILE *fp, midgard_alu_op op)
86 {
87 bool int_op = false;
88
89 if (alu_opcode_props[op].name) {
90 fprintf(fp, "%s", alu_opcode_props[op].name);
91
92 int_op = midgard_is_integer_op(op);
93 } else
94 fprintf(fp, "alu_op_%02X", op);
95
96 /* For constant analysis */
97 is_instruction_int = int_op;
98 }
99
100 static void
print_ld_st_opcode(FILE * fp,midgard_load_store_op op)101 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
102 {
103 if (load_store_opcode_props[op].name)
104 fprintf(fp, "%s", load_store_opcode_props[op].name);
105 else
106 fprintf(fp, "ldst_op_%02X", op);
107 }
108
109 static bool is_embedded_constant_half = false;
110 static bool is_embedded_constant_int = false;
111
112 static char
prefix_for_bits(unsigned bits)113 prefix_for_bits(unsigned bits)
114 {
115 switch (bits) {
116 case 8:
117 return 'q';
118 case 16:
119 return 'h';
120 case 64:
121 return 'd';
122 default:
123 return 0;
124 }
125 }
126
127 /* For static analysis to ensure all registers are written at least once before
128 * use along the source code path (TODO: does this break done for complex CF?)
129 */
130
131 uint16_t midg_ever_written = 0;
132
133 static void
print_reg(FILE * fp,unsigned reg,unsigned bits)134 print_reg(FILE *fp, unsigned reg, unsigned bits)
135 {
136 /* Perform basic static analysis for expanding constants correctly */
137
138 if (reg == 26) {
139 is_embedded_constant_int = is_instruction_int;
140 is_embedded_constant_half = (bits < 32);
141 }
142
143 unsigned uniform_reg = 23 - reg;
144 bool is_uniform = false;
145
146 /* For r8-r15, it could be a work or uniform. We distinguish based on
147 * the fact work registers are ALWAYS written before use, but uniform
148 * registers are NEVER written before use. */
149
150 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
151 is_uniform = true;
152
153 /* r16-r23 are always uniform */
154
155 if (reg >= 16 && reg <= 23)
156 is_uniform = true;
157
158 /* Update the uniform count appropriately */
159
160 if (is_uniform)
161 midg_stats.uniform_count =
162 MAX2(uniform_reg + 1, midg_stats.uniform_count);
163
164 char prefix = prefix_for_bits(bits);
165
166 if (prefix)
167 fputc(prefix, fp);
168
169 fprintf(fp, "r%u", reg);
170 }
171
172 static char *outmod_names_float[4] = {
173 "",
174 ".pos",
175 ".sat_signed",
176 ".sat"
177 };
178
179 static char *outmod_names_int[4] = {
180 ".isat",
181 ".usat",
182 "",
183 ".hi"
184 };
185
186 static char *srcmod_names_int[4] = {
187 "sext(",
188 "zext(",
189 "",
190 "("
191 };
192
193 static void
print_outmod(FILE * fp,unsigned outmod,bool is_int)194 print_outmod(FILE *fp, unsigned outmod, bool is_int)
195 {
196 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
197 outmod_names_float[outmod]);
198 }
199
200 static void
print_quad_word(FILE * fp,uint32_t * words,unsigned tabs)201 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
202 {
203 unsigned i;
204
205 for (i = 0; i < 4; i++)
206 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
207
208 fprintf(fp, "\n");
209 }
210
211 static const char components[16] = "xyzwefghijklmnop";
212
213 /* Helper to print 4 chars of a swizzle */
214 static void
print_swizzle_helper(FILE * fp,unsigned swizzle,unsigned offset)215 print_swizzle_helper(FILE *fp, unsigned swizzle, unsigned offset)
216 {
217 for (unsigned i = 0; i < 4; ++i) {
218 unsigned c = (swizzle >> (i * 2)) & 3;
219 c += offset;
220 fprintf(fp, "%c", components[c]);
221 }
222 }
223
224 /* Helper to print 8 chars of a swizzle, duplicating over */
225 static void
print_swizzle_helper_8(FILE * fp,unsigned swizzle,bool upper)226 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
227 {
228 for (unsigned i = 0; i < 4; ++i) {
229 unsigned c = (swizzle >> (i * 2)) & 3;
230 c *= 2;
231 c += upper*8;
232 fprintf(fp, "%c%c", components[c], components[c+1]);
233 }
234 }
235
236 static void
print_swizzle_vec16(FILE * fp,unsigned swizzle,bool rep_high,bool rep_low,midgard_dest_override override)237 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
238 midgard_dest_override override)
239 {
240 fprintf(fp, ".");
241
242 if (override == midgard_dest_override_upper) {
243 if (rep_high)
244 fprintf(fp, " /* rep_high */ ");
245 if (rep_low)
246 fprintf(fp, " /* rep_low */ ");
247
248 if (!rep_high && rep_low)
249 print_swizzle_helper_8(fp, swizzle, true);
250 else
251 print_swizzle_helper_8(fp, swizzle, false);
252 } else {
253 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
254 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
255 }
256 }
257
258 static void
print_swizzle_vec8(FILE * fp,unsigned swizzle,bool rep_high,bool rep_low,bool half)259 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
260 {
261 fprintf(fp, ".");
262
263 /* TODO: Is it possible to unify half/full? */
264
265 if (half) {
266 print_swizzle_helper(fp, swizzle, (rep_low * 8));
267 print_swizzle_helper(fp, swizzle, (rep_low * 8) + !rep_high * 4);
268 } else {
269 print_swizzle_helper(fp, swizzle, rep_high * 4);
270 print_swizzle_helper(fp, swizzle, !rep_low * 4);
271 }
272 }
273
274 static void
print_swizzle_vec4(FILE * fp,unsigned swizzle,bool rep_high,bool rep_low,bool half)275 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
276 {
277 if (rep_high)
278 fprintf(fp, " /* rep_high */ ");
279
280 if (!half && rep_low)
281 fprintf(fp, " /* rep_low */ ");
282
283 if (swizzle == 0xE4 && !half) return; /* xyzw */
284
285 fprintf(fp, ".");
286 print_swizzle_helper(fp, swizzle, rep_low * 4);
287 }
288 static void
print_swizzle_vec2(FILE * fp,unsigned swizzle,bool rep_high,bool rep_low,bool half)289 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
290 {
291 char *alphabet = "XY";
292
293 if (half) {
294 alphabet = rep_low ? "zw" : "xy";
295 } else if (rep_low)
296 fprintf(fp, " /* rep_low */ ");
297
298 if (rep_high)
299 fprintf(fp, " /* rep_high */ ");
300
301 if (swizzle == 0xE4 && !half) return; /* XY */
302
303 fprintf(fp, ".");
304
305 for (unsigned i = 0; i < 4; i += 2) {
306 unsigned a = (swizzle >> (i * 2)) & 3;
307 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
308
309 /* Normally we're adjacent, but if there's an issue, don't make
310 * it ambiguous */
311
312 if (b == (a + 1))
313 fprintf(fp, "%c", alphabet[a >> 1]);
314 else
315 fprintf(fp, "[%c%c]", components[a], components[b]);
316 }
317 }
318
319 static int
bits_for_mode(midgard_reg_mode mode)320 bits_for_mode(midgard_reg_mode mode)
321 {
322 switch (mode) {
323 case midgard_reg_mode_8:
324 return 8;
325 case midgard_reg_mode_16:
326 return 16;
327 case midgard_reg_mode_32:
328 return 32;
329 case midgard_reg_mode_64:
330 return 64;
331 default:
332 unreachable("Invalid reg mode");
333 return 0;
334 }
335 }
336
337 static int
bits_for_mode_halved(midgard_reg_mode mode,bool half)338 bits_for_mode_halved(midgard_reg_mode mode, bool half)
339 {
340 unsigned bits = bits_for_mode(mode);
341
342 if (half)
343 bits >>= 1;
344
345 return bits;
346 }
347
348 static void
print_scalar_constant(FILE * fp,unsigned src_binary,const midgard_constants * consts,midgard_scalar_alu * alu)349 print_scalar_constant(FILE *fp, unsigned src_binary,
350 const midgard_constants *consts,
351 midgard_scalar_alu *alu)
352 {
353 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
354 assert(consts != NULL);
355
356 fprintf(fp, "#");
357 mir_print_constant_component(fp, consts, src->component,
358 src->full ?
359 midgard_reg_mode_32 : midgard_reg_mode_16,
360 false, src->mod, alu->op);
361 }
362
363 static void
print_vector_constants(FILE * fp,unsigned src_binary,const midgard_constants * consts,midgard_vector_alu * alu)364 print_vector_constants(FILE *fp, unsigned src_binary,
365 const midgard_constants *consts,
366 midgard_vector_alu *alu)
367 {
368 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
369 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
370 unsigned max_comp = (sizeof(*consts) * 8) / bits;
371 unsigned comp_mask, num_comp = 0;
372
373 assert(consts);
374 assert(max_comp <= 16);
375
376 comp_mask = effective_writemask(alu->op, condense_writemask(alu->mask, bits));
377 num_comp = util_bitcount(comp_mask);
378
379 fprintf(fp, "<");
380 bool first = true;
381
382 for (unsigned i = 0; i < max_comp; ++i) {
383 if (!(comp_mask & (1 << i))) continue;
384
385 unsigned c = (src->swizzle >> (i * 2)) & 3;
386
387 if (bits == 16 && !src->half) {
388 if (i < 4)
389 c += (src->rep_high * 4);
390 else
391 c += (!src->rep_low * 4);
392 } else if (bits == 32 && !src->half) {
393 /* Implicitly ok */
394 } else if (bits == 8) {
395 assert (!src->half);
396 unsigned index = (i >> 1) & 3;
397 unsigned base = (src->swizzle >> (index * 2)) & 3;
398 c = base * 2;
399
400 if (i < 8)
401 c += (src->rep_high) * 8;
402 else
403 c += (!src->rep_low) * 8;
404
405 /* We work on twos, actually */
406 if (i & 1)
407 c++;
408 } else {
409 printf(" (%d%d%d)", src->rep_low, src->rep_high, src->half);
410 }
411
412 if (first)
413 first = false;
414 else
415 fprintf(fp, ", ");
416
417 mir_print_constant_component(fp, consts, c, alu->reg_mode,
418 src->half, src->mod, alu->op);
419 }
420
421 if (num_comp > 1)
422 fprintf(fp, ">");
423 }
424
425 static void
print_srcmod(FILE * fp,bool is_int,unsigned mod,bool scalar)426 print_srcmod(FILE *fp, bool is_int, unsigned mod, bool scalar)
427 {
428 /* Modifiers change meaning depending on the op's context */
429
430 midgard_int_mod int_mod = mod;
431
432 if (is_int) {
433 if (scalar && mod == 2) {
434 fprintf(fp, "unk2");
435 }
436
437 fprintf(fp, "%s", srcmod_names_int[int_mod]);
438 } else {
439 if (mod & MIDGARD_FLOAT_MOD_NEG)
440 fprintf(fp, "-");
441
442 if (mod & MIDGARD_FLOAT_MOD_ABS)
443 fprintf(fp, "abs(");
444 }
445 }
446
447 static void
print_srcmod_end(FILE * fp,bool is_int,unsigned mod,unsigned bits)448 print_srcmod_end(FILE *fp, bool is_int, unsigned mod, unsigned bits)
449 {
450 /* Since we wrapped with a function-looking thing */
451
452 if (is_int && mod == midgard_int_shift)
453 fprintf(fp, ") << %u", bits);
454 else if ((is_int && (mod != midgard_int_normal))
455 || (!is_int && mod & MIDGARD_FLOAT_MOD_ABS))
456 fprintf(fp, ")");
457 }
458
459 static void
print_vector_src(FILE * fp,unsigned src_binary,midgard_reg_mode mode,unsigned reg,midgard_dest_override override,bool is_int)460 print_vector_src(FILE *fp, unsigned src_binary,
461 midgard_reg_mode mode, unsigned reg,
462 midgard_dest_override override, bool is_int)
463 {
464 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
465 print_srcmod(fp, is_int, src->mod, false);
466
467 //register
468 unsigned bits = bits_for_mode_halved(mode, src->half);
469 print_reg(fp, reg, bits);
470
471 /* When the source was stepped down via `half`, rep_low means "higher
472 * half" and rep_high is never seen. When it's not native,
473 * rep_low/rep_high are for, well, replication */
474
475 if (mode == midgard_reg_mode_8) {
476 assert(!src->half);
477 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
478 } else if (mode == midgard_reg_mode_16) {
479 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
480 } else if (mode == midgard_reg_mode_32) {
481 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
482 } else if (mode == midgard_reg_mode_64) {
483 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
484 }
485
486 print_srcmod_end(fp, is_int, src->mod, bits);
487 }
488
489 static uint16_t
decode_vector_imm(unsigned src2_reg,unsigned imm)490 decode_vector_imm(unsigned src2_reg, unsigned imm)
491 {
492 uint16_t ret;
493 ret = src2_reg << 11;
494 ret |= (imm & 0x7) << 8;
495 ret |= (imm >> 3) & 0xFF;
496 return ret;
497 }
498
499 static void
print_immediate(FILE * fp,uint16_t imm)500 print_immediate(FILE *fp, uint16_t imm)
501 {
502 if (is_instruction_int)
503 fprintf(fp, "#%u", imm);
504 else
505 fprintf(fp, "#%g", _mesa_half_to_float(imm));
506 }
507
508 static void
update_dest(unsigned reg)509 update_dest(unsigned reg)
510 {
511 /* We should record writes as marking this as a work register. Store
512 * the max register in work_count; we'll add one at the end */
513
514 if (reg < 16) {
515 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
516 midg_ever_written |= (1 << reg);
517 }
518 }
519
520 static void
print_dest(FILE * fp,unsigned reg,midgard_reg_mode mode,midgard_dest_override override)521 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
522 {
523 /* Depending on the mode and override, we determine the type of
524 * destination addressed. Absent an override, we address just the
525 * type of the operation itself */
526
527 unsigned bits = bits_for_mode(mode);
528
529 if (override != midgard_dest_override_none)
530 bits /= 2;
531
532 update_dest(reg);
533 print_reg(fp, reg, bits);
534 }
535
536 static void
print_mask_vec16(FILE * fp,uint8_t mask,midgard_dest_override override)537 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
538 {
539 fprintf(fp, ".");
540
541 for (unsigned i = 0; i < 8; i++) {
542 if (mask & (1 << i))
543 fprintf(fp, "%c%c",
544 components[i*2 + 0],
545 components[i*2 + 1]);
546 }
547 }
548
549 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
550 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
551 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
552 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
553 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
554 * the mask to make it obvious what happened */
555
556 static void
print_mask(FILE * fp,uint8_t mask,unsigned bits,midgard_dest_override override)557 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
558 {
559 if (bits == 8) {
560 print_mask_vec16(fp, mask, override);
561 return;
562 }
563
564 /* Skip 'complete' masks */
565
566 if (override == midgard_dest_override_none)
567 if (bits >= 32 && mask == 0xFF) return;
568
569 fprintf(fp, ".");
570
571 unsigned skip = (bits / 16);
572 bool uppercase = bits > 32;
573 bool tripped = false;
574
575 /* To apply an upper destination override, we "shift" the alphabet.
576 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
577 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
578
579 const char *alphabet = components;
580
581 if (override == midgard_dest_override_upper)
582 alphabet += (128 / bits);
583
584 for (unsigned i = 0; i < 8; i += skip) {
585 bool a = (mask & (1 << i)) != 0;
586
587 for (unsigned j = 1; j < skip; ++j) {
588 bool dupe = (mask & (1 << (i + j))) != 0;
589 tripped |= (dupe != a);
590 }
591
592 if (a) {
593 char c = alphabet[i / skip];
594
595 if (uppercase)
596 c = toupper(c);
597
598 fprintf(fp, "%c", c);
599 }
600 }
601
602 if (tripped)
603 fprintf(fp, " /* %X */", mask);
604 }
605
606 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
607 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
608 * mode as well, but not load/store-style 16-bit mode. */
609
610 static void
print_mask_4(FILE * fp,unsigned mask,bool upper)611 print_mask_4(FILE *fp, unsigned mask, bool upper)
612 {
613 if (mask == 0xF) {
614 if (upper)
615 fprintf(fp, "'");
616
617 return;
618 }
619
620 fprintf(fp, ".");
621
622 for (unsigned i = 0; i < 4; ++i) {
623 bool a = (mask & (1 << i)) != 0;
624 if (a)
625 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
626 }
627 }
628
629 static void
print_vector_field(FILE * fp,const char * name,uint16_t * words,uint16_t reg_word,const midgard_constants * consts,unsigned tabs)630 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
631 const midgard_constants *consts, unsigned tabs)
632 {
633 midgard_reg_info *reg_info = (midgard_reg_info *)®_word;
634 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
635 midgard_reg_mode mode = alu_field->reg_mode;
636 unsigned override = alu_field->dest_override;
637
638 /* For now, prefix instruction names with their unit, until we
639 * understand how this works on a deeper level */
640 fprintf(fp, "%s.", name);
641
642 print_alu_opcode(fp, alu_field->op);
643
644 /* Postfix with the size to disambiguate if necessary */
645 char postfix = prefix_for_bits(bits_for_mode(mode));
646 bool size_ambiguous = override != midgard_dest_override_none;
647
648 if (size_ambiguous)
649 fprintf(fp, "%c", postfix ? postfix : 'r');
650
651 /* Print the outmod, if there is one */
652 print_outmod(fp, alu_field->outmod,
653 midgard_is_integer_out_op(alu_field->op));
654
655 fprintf(fp, " ");
656
657 /* Mask denoting status of 8-lanes */
658 uint8_t mask = alu_field->mask;
659
660 /* First, print the destination */
661 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
662
663 if (override != midgard_dest_override_none) {
664 bool modeable = (mode != midgard_reg_mode_8);
665 bool known = override != 0x3; /* Unused value */
666
667 if (!(modeable && known))
668 fprintf(fp, "/* do%u */ ", override);
669 }
670
671 /* Instructions like fdot4 do *not* replicate, ensure the
672 * mask is of only a single component */
673
674 unsigned rep = GET_CHANNEL_COUNT(alu_opcode_props[alu_field->op].props);
675
676 if (rep) {
677 unsigned comp_mask = condense_writemask(mask, bits_for_mode(mode));
678 unsigned num_comp = util_bitcount(comp_mask);
679 if (num_comp != 1)
680 fprintf(fp, "/* err too many components */");
681 }
682 print_mask(fp, mask, bits_for_mode(mode), override);
683
684 fprintf(fp, ", ");
685
686 bool is_int = midgard_is_integer_op(alu_field->op);
687
688 if (reg_info->src1_reg == 26)
689 print_vector_constants(fp, alu_field->src1, consts, alu_field);
690 else
691 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
692
693 fprintf(fp, ", ");
694
695 if (reg_info->src2_imm) {
696 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
697 print_immediate(fp, imm);
698 } else if (reg_info->src2_reg == 26) {
699 print_vector_constants(fp, alu_field->src2, consts, alu_field);
700 } else {
701 print_vector_src(fp, alu_field->src2, mode,
702 reg_info->src2_reg, override, is_int);
703 }
704
705 midg_stats.instruction_count++;
706 fprintf(fp, "\n");
707 }
708
709 static void
print_scalar_src(FILE * fp,bool is_int,unsigned src_binary,unsigned reg)710 print_scalar_src(FILE *fp, bool is_int, unsigned src_binary, unsigned reg)
711 {
712 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
713
714 print_srcmod(fp, is_int, src->mod, true);
715 print_reg(fp, reg, src->full ? 32 : 16);
716
717 unsigned c = src->component;
718
719 if (src->full) {
720 assert((c & 1) == 0);
721 c >>= 1;
722 }
723
724 fprintf(fp, ".%c", components[c]);
725
726 print_srcmod_end(fp, is_int, src->mod, src->full ? 32 : 16);
727 }
728
729 static uint16_t
decode_scalar_imm(unsigned src2_reg,unsigned imm)730 decode_scalar_imm(unsigned src2_reg, unsigned imm)
731 {
732 uint16_t ret;
733 ret = src2_reg << 11;
734 ret |= (imm & 3) << 9;
735 ret |= (imm & 4) << 6;
736 ret |= (imm & 0x38) << 2;
737 ret |= imm >> 6;
738 return ret;
739 }
740
741 static void
print_scalar_field(FILE * fp,const char * name,uint16_t * words,uint16_t reg_word,const midgard_constants * consts,unsigned tabs)742 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
743 const midgard_constants *consts, unsigned tabs)
744 {
745 midgard_reg_info *reg_info = (midgard_reg_info *)®_word;
746 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
747
748 if (alu_field->unknown)
749 fprintf(fp, "scalar ALU unknown bit set\n");
750
751 fprintf(fp, "%s.", name);
752 print_alu_opcode(fp, alu_field->op);
753 print_outmod(fp, alu_field->outmod,
754 midgard_is_integer_out_op(alu_field->op));
755 fprintf(fp, " ");
756
757 bool full = alu_field->output_full;
758 update_dest(reg_info->out_reg);
759 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
760 unsigned c = alu_field->output_component;
761 bool is_int = midgard_is_integer_op(alu_field->op);
762
763 if (full) {
764 assert((c & 1) == 0);
765 c >>= 1;
766 }
767
768 fprintf(fp, ".%c, ", components[c]);
769
770 if (reg_info->src1_reg == 26)
771 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
772 else
773 print_scalar_src(fp, is_int, alu_field->src1, reg_info->src1_reg);
774
775 fprintf(fp, ", ");
776
777 if (reg_info->src2_imm) {
778 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
779 alu_field->src2);
780 print_immediate(fp, imm);
781 } else if (reg_info->src2_reg == 26) {
782 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
783 } else
784 print_scalar_src(fp, is_int, alu_field->src2, reg_info->src2_reg);
785
786 midg_stats.instruction_count++;
787 fprintf(fp, "\n");
788 }
789
790 static void
print_branch_op(FILE * fp,unsigned op)791 print_branch_op(FILE *fp, unsigned op)
792 {
793 switch (op) {
794 case midgard_jmp_writeout_op_branch_uncond:
795 fprintf(fp, "uncond.");
796 break;
797
798 case midgard_jmp_writeout_op_branch_cond:
799 fprintf(fp, "cond.");
800 break;
801
802 case midgard_jmp_writeout_op_writeout:
803 fprintf(fp, "write.");
804 break;
805
806 case midgard_jmp_writeout_op_tilebuffer_pending:
807 fprintf(fp, "tilebuffer.");
808 break;
809
810 case midgard_jmp_writeout_op_discard:
811 fprintf(fp, "discard.");
812 break;
813
814 default:
815 fprintf(fp, "unk%u.", op);
816 break;
817 }
818 }
819
820 static void
print_branch_cond(FILE * fp,int cond)821 print_branch_cond(FILE *fp, int cond)
822 {
823 switch (cond) {
824 case midgard_condition_write0:
825 fprintf(fp, "write0");
826 break;
827
828 case midgard_condition_false:
829 fprintf(fp, "false");
830 break;
831
832 case midgard_condition_true:
833 fprintf(fp, "true");
834 break;
835
836 case midgard_condition_always:
837 fprintf(fp, "always");
838 break;
839
840 default:
841 fprintf(fp, "unk%X", cond);
842 break;
843 }
844 }
845
846 static bool
print_compact_branch_writeout_field(FILE * fp,uint16_t word)847 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
848 {
849 midgard_jmp_writeout_op op = word & 0x7;
850 midg_stats.instruction_count++;
851
852 switch (op) {
853 case midgard_jmp_writeout_op_branch_uncond: {
854 midgard_branch_uncond br_uncond;
855 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
856 fprintf(fp, "br.uncond ");
857
858 if (br_uncond.unknown != 1)
859 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
860
861 if (br_uncond.offset >= 0)
862 fprintf(fp, "+");
863
864 fprintf(fp, "%d -> %s", br_uncond.offset,
865 midgard_tag_props[br_uncond.dest_tag].name);
866 fprintf(fp, "\n");
867
868 return br_uncond.offset >= 0;
869 }
870
871 case midgard_jmp_writeout_op_branch_cond:
872 case midgard_jmp_writeout_op_writeout:
873 case midgard_jmp_writeout_op_discard:
874 default: {
875 midgard_branch_cond br_cond;
876 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
877
878 fprintf(fp, "br.");
879
880 print_branch_op(fp, br_cond.op);
881 print_branch_cond(fp, br_cond.cond);
882
883 fprintf(fp, " ");
884
885 if (br_cond.offset >= 0)
886 fprintf(fp, "+");
887
888 fprintf(fp, "%d -> %s", br_cond.offset,
889 midgard_tag_props[br_cond.dest_tag].name);
890 fprintf(fp, "\n");
891
892 return br_cond.offset >= 0;
893 }
894 }
895
896 return false;
897 }
898
899 static bool
print_extended_branch_writeout_field(FILE * fp,uint8_t * words,unsigned next)900 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
901 {
902 midgard_branch_extended br;
903 memcpy((char *) &br, (char *) words, sizeof(br));
904
905 fprintf(fp, "brx.");
906
907 print_branch_op(fp, br.op);
908
909 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
910
911 bool single_channel = true;
912
913 for (unsigned i = 0; i < 16; i += 2) {
914 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
915 }
916
917 if (single_channel)
918 print_branch_cond(fp, br.cond & 0x3);
919 else
920 fprintf(fp, "lut%X", br.cond);
921
922 if (br.unknown)
923 fprintf(fp, ".unknown%u", br.unknown);
924
925 fprintf(fp, " ");
926
927 if (br.offset >= 0)
928 fprintf(fp, "+");
929
930 fprintf(fp, "%d -> %s\n", br.offset,
931 midgard_tag_props[br.dest_tag].name);
932
933 unsigned I = next + br.offset * 4;
934
935 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
936 fprintf(fp, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
937 midgard_tag_props[br.dest_tag].name,
938 midgard_tag_props[midg_tags[I]].name);
939 }
940
941 midg_tags[I] = br.dest_tag;
942
943 midg_stats.instruction_count++;
944 return br.offset >= 0;
945 }
946
947 static unsigned
num_alu_fields_enabled(uint32_t control_word)948 num_alu_fields_enabled(uint32_t control_word)
949 {
950 unsigned ret = 0;
951
952 if ((control_word >> 17) & 1)
953 ret++;
954
955 if ((control_word >> 19) & 1)
956 ret++;
957
958 if ((control_word >> 21) & 1)
959 ret++;
960
961 if ((control_word >> 23) & 1)
962 ret++;
963
964 if ((control_word >> 25) & 1)
965 ret++;
966
967 return ret;
968 }
969
970 static bool
print_alu_word(FILE * fp,uint32_t * words,unsigned num_quad_words,unsigned tabs,unsigned next)971 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
972 unsigned tabs, unsigned next)
973 {
974 uint32_t control_word = words[0];
975 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
976 unsigned num_fields = num_alu_fields_enabled(control_word);
977 uint16_t *word_ptr = beginning_ptr + num_fields;
978 unsigned num_words = 2 + num_fields;
979 const midgard_constants *consts = NULL;
980 bool branch_forward = false;
981
982 if ((control_word >> 17) & 1)
983 num_words += 3;
984
985 if ((control_word >> 19) & 1)
986 num_words += 2;
987
988 if ((control_word >> 21) & 1)
989 num_words += 3;
990
991 if ((control_word >> 23) & 1)
992 num_words += 2;
993
994 if ((control_word >> 25) & 1)
995 num_words += 3;
996
997 if ((control_word >> 26) & 1)
998 num_words += 1;
999
1000 if ((control_word >> 27) & 1)
1001 num_words += 3;
1002
1003 if (num_quad_words > (num_words + 7) / 8) {
1004 assert(num_quad_words == (num_words + 15) / 8);
1005 //Assume that the extra quadword is constants
1006 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
1007 }
1008
1009 if ((control_word >> 16) & 1)
1010 fprintf(fp, "unknown bit 16 enabled\n");
1011
1012 if ((control_word >> 17) & 1) {
1013 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
1014 beginning_ptr += 1;
1015 word_ptr += 3;
1016 }
1017
1018 if ((control_word >> 18) & 1)
1019 fprintf(fp, "unknown bit 18 enabled\n");
1020
1021 if ((control_word >> 19) & 1) {
1022 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
1023 beginning_ptr += 1;
1024 word_ptr += 2;
1025 }
1026
1027 if ((control_word >> 20) & 1)
1028 fprintf(fp, "unknown bit 20 enabled\n");
1029
1030 if ((control_word >> 21) & 1) {
1031 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
1032 beginning_ptr += 1;
1033 word_ptr += 3;
1034 }
1035
1036 if ((control_word >> 22) & 1)
1037 fprintf(fp, "unknown bit 22 enabled\n");
1038
1039 if ((control_word >> 23) & 1) {
1040 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
1041 beginning_ptr += 1;
1042 word_ptr += 2;
1043 }
1044
1045 if ((control_word >> 24) & 1)
1046 fprintf(fp, "unknown bit 24 enabled\n");
1047
1048 if ((control_word >> 25) & 1) {
1049 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
1050 word_ptr += 3;
1051 }
1052
1053 if ((control_word >> 26) & 1) {
1054 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
1055 word_ptr += 1;
1056 }
1057
1058 if ((control_word >> 27) & 1) {
1059 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
1060 word_ptr += 3;
1061 }
1062
1063 if (consts)
1064 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1065 consts->u32[0], consts->u32[1],
1066 consts->u32[2], consts->u32[3]);
1067
1068 return branch_forward;
1069 }
1070
1071 static void
print_varying_parameters(FILE * fp,midgard_load_store_word * word)1072 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1073 {
1074 midgard_varying_parameter param;
1075 unsigned v = word->varying_parameters;
1076 memcpy(¶m, &v, sizeof(param));
1077
1078 if (param.is_varying) {
1079 /* If a varying, there are qualifiers */
1080 if (param.flat)
1081 fprintf(fp, ".flat");
1082
1083 if (param.interpolation != midgard_interp_default) {
1084 if (param.interpolation == midgard_interp_centroid)
1085 fprintf(fp, ".centroid");
1086 else if (param.interpolation == midgard_interp_sample)
1087 fprintf(fp, ".sample");
1088 else
1089 fprintf(fp, ".interp%d", param.interpolation);
1090 }
1091
1092 if (param.modifier != midgard_varying_mod_none) {
1093 if (param.modifier == midgard_varying_mod_perspective_w)
1094 fprintf(fp, ".perspectivew");
1095 else if (param.modifier == midgard_varying_mod_perspective_z)
1096 fprintf(fp, ".perspectivez");
1097 else
1098 fprintf(fp, ".mod%d", param.modifier);
1099 }
1100 } else if (param.flat || param.interpolation || param.modifier) {
1101 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1102 }
1103
1104 if (param.zero0 || param.zero1 || param.zero2)
1105 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1106 }
1107
1108 static bool
is_op_varying(unsigned op)1109 is_op_varying(unsigned op)
1110 {
1111 switch (op) {
1112 case midgard_op_st_vary_16:
1113 case midgard_op_st_vary_32:
1114 case midgard_op_st_vary_32i:
1115 case midgard_op_st_vary_32u:
1116 case midgard_op_ld_vary_16:
1117 case midgard_op_ld_vary_32:
1118 case midgard_op_ld_vary_32i:
1119 case midgard_op_ld_vary_32u:
1120 return true;
1121 }
1122
1123 return false;
1124 }
1125
1126 static bool
is_op_attribute(unsigned op)1127 is_op_attribute(unsigned op)
1128 {
1129 switch (op) {
1130 case midgard_op_ld_attr_16:
1131 case midgard_op_ld_attr_32:
1132 case midgard_op_ld_attr_32i:
1133 case midgard_op_ld_attr_32u:
1134 return true;
1135 }
1136
1137 return false;
1138 }
1139
1140 static void
print_load_store_arg(FILE * fp,uint8_t arg,unsigned index)1141 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1142 {
1143 /* Try to interpret as a register */
1144 midgard_ldst_register_select sel;
1145 memcpy(&sel, &arg, sizeof(arg));
1146
1147 /* If unknown is set, we're not sure what this is or how to
1148 * interpret it. But if it's zero, we get it. */
1149
1150 if (sel.unknown) {
1151 fprintf(fp, "0x%02X", arg);
1152 return;
1153 }
1154
1155 unsigned reg = REGISTER_LDST_BASE + sel.select;
1156 char comp = components[sel.component];
1157
1158 fprintf(fp, "r%u.%c", reg, comp);
1159
1160 /* Only print a shift if it's non-zero. Shifts only make sense for the
1161 * second index. For the first, we're not sure what it means yet */
1162
1163 if (index == 1) {
1164 if (sel.shift)
1165 fprintf(fp, " << %u", sel.shift);
1166 } else {
1167 fprintf(fp, " /* %X */", sel.shift);
1168 }
1169 }
1170
1171 static void
update_stats(signed * stat,unsigned address)1172 update_stats(signed *stat, unsigned address)
1173 {
1174 if (*stat >= 0)
1175 *stat = MAX2(*stat, address + 1);
1176 }
1177
1178 static void
print_load_store_instr(FILE * fp,uint64_t data,unsigned tabs)1179 print_load_store_instr(FILE *fp, uint64_t data,
1180 unsigned tabs)
1181 {
1182 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1183
1184 print_ld_st_opcode(fp, word->op);
1185
1186 unsigned address = word->address;
1187
1188 if (is_op_varying(word->op)) {
1189 print_varying_parameters(fp, word);
1190
1191 /* Do some analysis: check if direct cacess */
1192
1193 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1194 update_stats(&midg_stats.varying_count, address);
1195 else
1196 midg_stats.varying_count = -16;
1197 } else if (is_op_attribute(word->op)) {
1198 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1199 update_stats(&midg_stats.attribute_count, address);
1200 else
1201 midg_stats.attribute_count = -16;
1202 }
1203
1204 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1205 print_mask_4(fp, word->mask, false);
1206
1207 if (!OP_IS_STORE(word->op))
1208 update_dest(word->reg);
1209
1210 bool is_ubo = OP_IS_UBO_READ(word->op);
1211
1212 if (is_ubo) {
1213 /* UBOs use their own addressing scheme */
1214
1215 int lo = word->varying_parameters >> 7;
1216 int hi = word->address;
1217
1218 /* TODO: Combine fields logically */
1219 address = (hi << 3) | lo;
1220 }
1221
1222 fprintf(fp, ", %u", address);
1223
1224 print_swizzle_vec4(fp, word->swizzle, false, false, false);
1225
1226 fprintf(fp, ", ");
1227
1228 if (is_ubo) {
1229 fprintf(fp, "ubo%u", word->arg_1);
1230 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1231 } else
1232 print_load_store_arg(fp, word->arg_1, 0);
1233
1234 fprintf(fp, ", ");
1235 print_load_store_arg(fp, word->arg_2, 1);
1236 fprintf(fp, " /* %X */\n", word->varying_parameters);
1237
1238 midg_stats.instruction_count++;
1239 }
1240
1241 static void
print_load_store_word(FILE * fp,uint32_t * word,unsigned tabs)1242 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1243 {
1244 midgard_load_store *load_store = (midgard_load_store *) word;
1245
1246 if (load_store->word1 != 3) {
1247 print_load_store_instr(fp, load_store->word1, tabs);
1248 }
1249
1250 if (load_store->word2 != 3) {
1251 print_load_store_instr(fp, load_store->word2, tabs);
1252 }
1253 }
1254
1255 static void
print_texture_reg_select(FILE * fp,uint8_t u,unsigned base)1256 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1257 {
1258 midgard_tex_register_select sel;
1259 memcpy(&sel, &u, sizeof(u));
1260
1261 if (!sel.full)
1262 fprintf(fp, "h");
1263
1264 fprintf(fp, "r%u", base + sel.select);
1265
1266 unsigned component = sel.component;
1267
1268 /* Use the upper half in half-reg mode */
1269 if (sel.upper) {
1270 assert(!sel.full);
1271 component += 4;
1272 }
1273
1274 fprintf(fp, ".%c", components[component]);
1275
1276 assert(sel.zero == 0);
1277 }
1278
1279 static void
print_texture_format(FILE * fp,int format)1280 print_texture_format(FILE *fp, int format)
1281 {
1282 /* Act like a modifier */
1283 fprintf(fp, ".");
1284
1285 switch (format) {
1286 DEFINE_CASE(1, "1d");
1287 DEFINE_CASE(2, "2d");
1288 DEFINE_CASE(3, "3d");
1289 DEFINE_CASE(0, "cube");
1290
1291 default:
1292 unreachable("Bad format");
1293 }
1294 }
1295
1296 static bool
midgard_op_has_helpers(unsigned op)1297 midgard_op_has_helpers(unsigned op)
1298 {
1299 switch (op) {
1300 case TEXTURE_OP_NORMAL:
1301 case TEXTURE_OP_DERIVATIVE:
1302 return true;
1303 default:
1304 return false;
1305 }
1306 }
1307
1308 static void
print_texture_op(FILE * fp,unsigned op)1309 print_texture_op(FILE *fp, unsigned op)
1310 {
1311 switch (op) {
1312 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1313 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1314 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1315 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1316 DEFINE_CASE(TEXTURE_OP_DERIVATIVE, "derivative");
1317
1318 default:
1319 fprintf(fp, "tex_%X", op);
1320 break;
1321 }
1322 }
1323
1324 static bool
texture_op_takes_bias(unsigned op)1325 texture_op_takes_bias(unsigned op)
1326 {
1327 return op == TEXTURE_OP_NORMAL;
1328 }
1329
1330 static char
sampler_type_name(enum mali_sampler_type t)1331 sampler_type_name(enum mali_sampler_type t)
1332 {
1333 switch (t) {
1334 case MALI_SAMPLER_FLOAT:
1335 return 'f';
1336 case MALI_SAMPLER_UNSIGNED:
1337 return 'u';
1338 case MALI_SAMPLER_SIGNED:
1339 return 'i';
1340 default:
1341 return '?';
1342 }
1343
1344 }
1345
1346 static void
print_texture_barrier(FILE * fp,uint32_t * word)1347 print_texture_barrier(FILE *fp, uint32_t *word)
1348 {
1349 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1350
1351 if (barrier->type != TAG_TEXTURE_4_BARRIER)
1352 fprintf(fp, "/* barrier tag %X != tex/bar */ ", barrier->type);
1353
1354 if (!barrier->cont)
1355 fprintf(fp, "/* cont missing? */");
1356
1357 if (!barrier->last)
1358 fprintf(fp, "/* last missing? */");
1359
1360 if (barrier->zero1)
1361 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1362
1363 if (barrier->zero2)
1364 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1365
1366 if (barrier->zero3)
1367 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1368
1369 if (barrier->zero4)
1370 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1371
1372 if (barrier->zero5)
1373 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1374
1375 if (barrier->out_of_order)
1376 fprintf(fp, ".ooo%u", barrier->out_of_order);
1377
1378 fprintf(fp, "\n");
1379 }
1380
1381 #undef DEFINE_CASE
1382
1383 static const char *
texture_mode(enum mali_texture_mode mode)1384 texture_mode(enum mali_texture_mode mode)
1385 {
1386 switch (mode) {
1387 case TEXTURE_NORMAL: return "";
1388 case TEXTURE_SHADOW: return ".shadow";
1389 case TEXTURE_GATHER_SHADOW: return ".gather.shadow";
1390 case TEXTURE_GATHER_X: return ".gatherX";
1391 case TEXTURE_GATHER_Y: return ".gatherY";
1392 case TEXTURE_GATHER_Z: return ".gatherZ";
1393 case TEXTURE_GATHER_W: return ".gatherW";
1394 default: return "unk";
1395 }
1396 }
1397
1398 static const char *
derivative_mode(enum mali_derivative_mode mode)1399 derivative_mode(enum mali_derivative_mode mode)
1400 {
1401 switch (mode) {
1402 case TEXTURE_DFDX: return ".x";
1403 case TEXTURE_DFDY: return ".y";
1404 default: return "unk";
1405 }
1406 }
1407
1408 static void
print_texture_word(FILE * fp,uint32_t * word,unsigned tabs,unsigned in_reg_base,unsigned out_reg_base)1409 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1410 {
1411 midgard_texture_word *texture = (midgard_texture_word *) word;
1412 midg_stats.helper_invocations |= midgard_op_has_helpers(texture->op);
1413
1414 /* Broad category of texture operation in question */
1415 print_texture_op(fp, texture->op);
1416
1417 /* Barriers use a dramatically different code path */
1418 if (texture->op == TEXTURE_OP_BARRIER) {
1419 print_texture_barrier(fp, word);
1420 return;
1421 } else if (texture->type == TAG_TEXTURE_4_BARRIER)
1422 fprintf (fp, "/* nonbarrier had tex/bar tag */ ");
1423 else if (texture->type == TAG_TEXTURE_4_VTX)
1424 fprintf (fp, ".vtx");
1425
1426 if (texture->op == TEXTURE_OP_DERIVATIVE)
1427 fprintf(fp, "%s", derivative_mode(texture->mode));
1428 else
1429 fprintf(fp, "%s", texture_mode(texture->mode));
1430
1431 /* Specific format in question */
1432 print_texture_format(fp, texture->format);
1433
1434 /* Instruction "modifiers" parallel the ALU instructions. */
1435
1436 if (texture->cont)
1437 fprintf(fp, ".cont");
1438
1439 if (texture->last)
1440 fprintf(fp, ".last");
1441
1442 if (texture->out_of_order)
1443 fprintf(fp, ".ooo%u", texture->out_of_order);
1444
1445 /* Output modifiers are always interpreted floatly */
1446 print_outmod(fp, texture->outmod, false);
1447
1448 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1449 out_reg_base + texture->out_reg_select);
1450 print_mask_4(fp, texture->mask, texture->out_upper);
1451 assert(!(texture->out_full && texture->out_upper));
1452 fprintf(fp, ", ");
1453
1454 /* Depending on whether we read from textures directly or indirectly,
1455 * we may be able to update our analysis */
1456
1457 if (texture->texture_register) {
1458 fprintf(fp, "texture[");
1459 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1460 fprintf(fp, "], ");
1461
1462 /* Indirect, tut tut */
1463 midg_stats.texture_count = -16;
1464 } else {
1465 fprintf(fp, "texture%u, ", texture->texture_handle);
1466 update_stats(&midg_stats.texture_count, texture->texture_handle);
1467 }
1468
1469 /* Print the type, GL style */
1470 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1471
1472 if (texture->sampler_register) {
1473 fprintf(fp, "[");
1474 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1475 fprintf(fp, "]");
1476
1477 midg_stats.sampler_count = -16;
1478 } else {
1479 fprintf(fp, "%u", texture->sampler_handle);
1480 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1481 }
1482
1483 print_swizzle_vec4(fp, texture->swizzle, false, false, false);
1484 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1485 assert(!(texture->in_reg_full && texture->in_reg_upper));
1486
1487 /* TODO: integrate with swizzle */
1488 if (texture->in_reg_upper)
1489 fprintf(fp, "'");
1490
1491 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false, false);
1492
1493 /* There is *always* an offset attached. Of
1494 * course, that offset is just immediate #0 for a
1495 * GLES call that doesn't take an offset. If there
1496 * is a non-negative non-zero offset, this is
1497 * specified in immediate offset mode, with the
1498 * values in the offset_* fields as immediates. If
1499 * this is a negative offset, we instead switch to
1500 * a register offset mode, where the offset_*
1501 * fields become register triplets */
1502
1503 if (texture->offset_register) {
1504 fprintf(fp, " + ");
1505
1506 bool full = texture->offset & 1;
1507 bool select = texture->offset & 2;
1508 bool upper = texture->offset & 4;
1509
1510 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1511 assert(!(texture->out_full && texture->out_upper));
1512
1513 /* TODO: integrate with swizzle */
1514 if (upper)
1515 fprintf(fp, "'");
1516
1517 print_swizzle_vec4(fp, texture->offset >> 3, false, false, false);
1518
1519 fprintf(fp, ", ");
1520 } else if (texture->offset) {
1521 /* Only select ops allow negative immediate offsets, verify */
1522
1523 signed offset_x = (texture->offset & 0xF);
1524 signed offset_y = ((texture->offset >> 4) & 0xF);
1525 signed offset_z = ((texture->offset >> 8) & 0xF);
1526
1527 bool neg_x = offset_x < 0;
1528 bool neg_y = offset_y < 0;
1529 bool neg_z = offset_z < 0;
1530 bool any_neg = neg_x || neg_y || neg_z;
1531
1532 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1533 fprintf(fp, "/* invalid negative */ ");
1534
1535 /* Regardless, just print the immediate offset */
1536
1537 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1538 } else {
1539 fprintf(fp, ", ");
1540 }
1541
1542 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1543
1544 if (texture->lod_register) {
1545 fprintf(fp, "lod %c ", lod_operand);
1546 print_texture_reg_select(fp, texture->bias, in_reg_base);
1547 fprintf(fp, ", ");
1548
1549 if (texture->bias_int)
1550 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1551 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1552 /* For texel fetch, the int LOD is in the fractional place and
1553 * there is no fraction. We *always* have an explicit LOD, even
1554 * if it's zero. */
1555
1556 if (texture->bias_int)
1557 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1558
1559 fprintf(fp, "lod = %u, ", texture->bias);
1560 } else if (texture->bias || texture->bias_int) {
1561 signed bias_int = texture->bias_int;
1562 float bias_frac = texture->bias / 256.0f;
1563 float bias = bias_int + bias_frac;
1564
1565 bool is_bias = texture_op_takes_bias(texture->op);
1566 char sign = (bias >= 0.0) ? '+' : '-';
1567 char operand = is_bias ? sign : '=';
1568
1569 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1570 }
1571
1572 fprintf(fp, "\n");
1573
1574 /* While not zero in general, for these simple instructions the
1575 * following unknowns are zero, so we don't include them */
1576
1577 if (texture->unknown4 ||
1578 texture->unknown8) {
1579 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1580 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1581 }
1582
1583 midg_stats.instruction_count++;
1584 }
1585
1586 struct midgard_disasm_stats
disassemble_midgard(FILE * fp,uint8_t * code,size_t size,unsigned gpu_id,gl_shader_stage stage)1587 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1588 {
1589 uint32_t *words = (uint32_t *) code;
1590 unsigned num_words = size / 4;
1591 int tabs = 0;
1592
1593 bool branch_forward = false;
1594
1595 int last_next_tag = -1;
1596
1597 unsigned i = 0;
1598
1599 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1600
1601 /* Stats for shader-db */
1602 memset(&midg_stats, 0, sizeof(midg_stats));
1603 midg_ever_written = 0;
1604
1605 while (i < num_words) {
1606 unsigned tag = words[i] & 0xF;
1607 unsigned next_tag = (words[i] >> 4) & 0xF;
1608 unsigned num_quad_words = midgard_tag_props[tag].size;
1609
1610 if (midg_tags[i] && midg_tags[i] != tag) {
1611 fprintf(fp, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1612 midgard_tag_props[tag].name,
1613 midgard_tag_props[midg_tags[i]].name);
1614 }
1615
1616 midg_tags[i] = tag;
1617
1618 /* Check the tag. The idea is to ensure that next_tag is
1619 * *always* recoverable from the disassembly, such that we may
1620 * safely omit printing next_tag. To show this, we first
1621 * consider that next tags are semantically off-byone -- we end
1622 * up parsing tag n during step n+1. So, we ensure after we're
1623 * done disassembling the next tag of the final bundle is BREAK
1624 * and warn otherwise. We also ensure that the next tag is
1625 * never INVALID. Beyond that, since the last tag is checked
1626 * outside the loop, we can check one tag prior. If equal to
1627 * the current tag (which is unique), we're done. Otherwise, we
1628 * print if that tag was > TAG_BREAK, which implies the tag was
1629 * not TAG_BREAK or TAG_INVALID. But we already checked for
1630 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1631 * we're silent. So we throw in a print for break-next on at
1632 * the end of the bundle (if it's not the final bundle, which
1633 * we already check for above), disambiguating this case as
1634 * well. Hence in all cases we are unambiguous, QED. */
1635
1636 if (next_tag == TAG_INVALID)
1637 fprintf(fp, "\t/* XXX: invalid next tag */\n");
1638
1639 if (last_next_tag > TAG_BREAK && last_next_tag != tag) {
1640 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1641 midgard_tag_props[tag].name,
1642 midgard_tag_props[last_next_tag].name);
1643 }
1644
1645 last_next_tag = next_tag;
1646
1647 /* Tags are unique in the following way:
1648 *
1649 * INVALID, BREAK, UNKNOWN_*: verbosely printed
1650 * TEXTURE_4_BARRIER: verified by barrier/!barrier op
1651 * TEXTURE_4_VTX: .vtx tag printed
1652 * TEXTURE_4: tetxure lack of barriers or .vtx
1653 * TAG_LOAD_STORE_4: only load/store
1654 * TAG_ALU_4/8/12/16: by number of instructions/constants
1655 * TAG_ALU_4_8/12/16_WRITEOUT: ^^ with .writeout tag
1656 */
1657
1658 switch (tag) {
1659 case TAG_TEXTURE_4_VTX ... TAG_TEXTURE_4_BARRIER: {
1660 bool interpipe_aliasing =
1661 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1662
1663 print_texture_word(fp, &words[i], tabs,
1664 interpipe_aliasing ? 0 : REG_TEX_BASE,
1665 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1666 break;
1667 }
1668
1669 case TAG_LOAD_STORE_4:
1670 print_load_store_word(fp, &words[i], tabs);
1671 break;
1672
1673 case TAG_ALU_4 ... TAG_ALU_16_WRITEOUT:
1674 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1675
1676 /* Reset word static analysis state */
1677 is_embedded_constant_half = false;
1678 is_embedded_constant_int = false;
1679
1680 /* TODO: infer/verify me */
1681 if (tag >= TAG_ALU_4_WRITEOUT)
1682 fprintf(fp, "writeout\n");
1683
1684 break;
1685
1686 default:
1687 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1688 num_quad_words = 1;
1689 print_quad_word(fp, &words[i], tabs);
1690 fprintf(fp, "\n");
1691 break;
1692 }
1693
1694 /* We are parsing per bundle anyway. Add before we start
1695 * breaking out so we don't miss the final bundle. */
1696
1697 midg_stats.bundle_count++;
1698 midg_stats.quadword_count += num_quad_words;
1699
1700 /* Include a synthetic "break" instruction at the end of the
1701 * bundle to signify that if, absent a branch, the shader
1702 * execution will stop here. Stop disassembly at such a break
1703 * based on a heuristic */
1704
1705 if (next_tag == TAG_BREAK) {
1706 if (branch_forward) {
1707 fprintf(fp, "break\n");
1708 } else {
1709 fprintf(fp, "\n");
1710 break;
1711 }
1712 }
1713
1714 fprintf(fp, "\n");
1715
1716 i += 4 * num_quad_words;
1717 }
1718
1719 if (last_next_tag != TAG_BREAK) {
1720 fprintf(fp, "/* XXX: shader ended with tag %s */\n",
1721 midgard_tag_props[last_next_tag].name);
1722 }
1723
1724 free(midg_tags);
1725
1726 /* We computed work_count as max_work_registers, so add one to get the
1727 * count. If no work registers are written, you still have one work
1728 * reported, which is exactly what the hardware expects */
1729
1730 midg_stats.work_count++;
1731
1732 return midg_stats;
1733 }
1734