1 /*
2  * Copyright © 2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "nir.h"
25 #include "nir_deref.h"
26 #include "main/menums.h"
27 
28 static bool
src_is_invocation_id(const nir_src * src)29 src_is_invocation_id(const nir_src *src)
30 {
31    assert(src->is_ssa);
32    if (src->ssa->parent_instr->type != nir_instr_type_intrinsic)
33       return false;
34 
35    return nir_instr_as_intrinsic(src->ssa->parent_instr)->intrinsic ==
36              nir_intrinsic_load_invocation_id;
37 }
38 
39 static void
get_deref_info(nir_shader * shader,nir_variable * var,nir_deref_instr * deref,bool * cross_invocation,bool * indirect)40 get_deref_info(nir_shader *shader, nir_variable *var, nir_deref_instr *deref,
41                bool *cross_invocation, bool *indirect)
42 {
43    *cross_invocation = false;
44    *indirect = false;
45 
46    const bool per_vertex = nir_is_per_vertex_io(var, shader->info.stage);
47 
48    nir_deref_path path;
49    nir_deref_path_init(&path, deref, NULL);
50    assert(path.path[0]->deref_type == nir_deref_type_var);
51    nir_deref_instr **p = &path.path[1];
52 
53    /* Vertex index is the outermost array index. */
54    if (per_vertex) {
55       assert((*p)->deref_type == nir_deref_type_array);
56       nir_instr *vertex_index_instr = (*p)->arr.index.ssa->parent_instr;
57       *cross_invocation =
58          vertex_index_instr->type != nir_instr_type_intrinsic ||
59          nir_instr_as_intrinsic(vertex_index_instr)->intrinsic !=
60             nir_intrinsic_load_invocation_id;
61       p++;
62    }
63 
64    /* We always lower indirect dereferences for "compact" array vars. */
65    if (!path.path[0]->var->data.compact) {
66       /* Non-compact array vars: find out if they are indirect. */
67       for (; *p; p++) {
68          if ((*p)->deref_type == nir_deref_type_array) {
69             *indirect |= !nir_src_is_const((*p)->arr.index);
70          } else if ((*p)->deref_type == nir_deref_type_struct) {
71             /* Struct indices are always constant. */
72          } else {
73             unreachable("Unsupported deref type");
74          }
75       }
76    }
77 
78    nir_deref_path_finish(&path);
79 }
80 
81 static void
set_io_mask(nir_shader * shader,nir_variable * var,int offset,int len,nir_deref_instr * deref,bool is_output_read)82 set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
83             nir_deref_instr *deref, bool is_output_read)
84 {
85    for (int i = 0; i < len; i++) {
86       assert(var->data.location != -1);
87 
88       int idx = var->data.location + offset + i;
89       bool is_patch_generic = var->data.patch &&
90                               idx != VARYING_SLOT_TESS_LEVEL_INNER &&
91                               idx != VARYING_SLOT_TESS_LEVEL_OUTER &&
92                               idx != VARYING_SLOT_BOUNDING_BOX0 &&
93                               idx != VARYING_SLOT_BOUNDING_BOX1;
94       uint64_t bitfield;
95 
96       if (is_patch_generic) {
97          assert(idx >= VARYING_SLOT_PATCH0 && idx < VARYING_SLOT_TESS_MAX);
98          bitfield = BITFIELD64_BIT(idx - VARYING_SLOT_PATCH0);
99       }
100       else {
101          assert(idx < VARYING_SLOT_MAX);
102          bitfield = BITFIELD64_BIT(idx);
103       }
104 
105       bool cross_invocation;
106       bool indirect;
107       get_deref_info(shader, var, deref, &cross_invocation, &indirect);
108 
109       if (var->data.mode == nir_var_shader_in) {
110          if (is_patch_generic) {
111             shader->info.patch_inputs_read |= bitfield;
112             if (indirect)
113                shader->info.patch_inputs_read_indirectly |= bitfield;
114          } else {
115             shader->info.inputs_read |= bitfield;
116             if (indirect)
117                shader->info.inputs_read_indirectly |= bitfield;
118          }
119 
120          if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
121             shader->info.tess.tcs_cross_invocation_inputs_read |= bitfield;
122 
123          if (shader->info.stage == MESA_SHADER_FRAGMENT) {
124             shader->info.fs.uses_sample_qualifier |= var->data.sample;
125          }
126       } else {
127          assert(var->data.mode == nir_var_shader_out);
128          if (is_output_read) {
129             if (is_patch_generic) {
130                shader->info.patch_outputs_read |= bitfield;
131                if (indirect)
132                   shader->info.patch_outputs_accessed_indirectly |= bitfield;
133             } else {
134                shader->info.outputs_read |= bitfield;
135                if (indirect)
136                   shader->info.outputs_accessed_indirectly |= bitfield;
137             }
138 
139             if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
140                shader->info.tess.tcs_cross_invocation_outputs_read |= bitfield;
141          } else {
142             if (is_patch_generic) {
143                shader->info.patch_outputs_written |= bitfield;
144                if (indirect)
145                   shader->info.patch_outputs_accessed_indirectly |= bitfield;
146             } else if (!var->data.read_only) {
147                shader->info.outputs_written |= bitfield;
148                if (indirect)
149                   shader->info.outputs_accessed_indirectly |= bitfield;
150             }
151          }
152 
153 
154          if (var->data.fb_fetch_output) {
155             shader->info.outputs_read |= bitfield;
156             if (shader->info.stage == MESA_SHADER_FRAGMENT)
157                shader->info.fs.uses_fbfetch_output = true;
158          }
159 
160          if (shader->info.stage == MESA_SHADER_FRAGMENT &&
161              !is_output_read && var->data.index == 1)
162             shader->info.fs.color_is_dual_source = true;
163       }
164    }
165 }
166 
167 /**
168  * Mark an entire variable as used.  Caller must ensure that the variable
169  * represents a shader input or output.
170  */
171 static void
mark_whole_variable(nir_shader * shader,nir_variable * var,nir_deref_instr * deref,bool is_output_read)172 mark_whole_variable(nir_shader *shader, nir_variable *var,
173                     nir_deref_instr *deref, bool is_output_read)
174 {
175    const struct glsl_type *type = var->type;
176 
177    if (nir_is_per_vertex_io(var, shader->info.stage)) {
178       assert(glsl_type_is_array(type));
179       type = glsl_get_array_element(type);
180    }
181 
182    if (var->data.per_view) {
183       /* TODO: Per view and Per Vertex are not currently used together.  When
184        * they start to be used (e.g. when adding Primitive Replication for GS
185        * on Intel), verify that "peeling" the type twice is correct.  This
186        * assert ensures we remember it.
187        */
188       assert(!nir_is_per_vertex_io(var, shader->info.stage));
189       assert(glsl_type_is_array(type));
190       type = glsl_get_array_element(type);
191    }
192 
193    const unsigned slots =
194       var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
195                         : glsl_count_attribute_slots(type, false);
196 
197    set_io_mask(shader, var, 0, slots, deref, is_output_read);
198 }
199 
200 static unsigned
get_io_offset(nir_deref_instr * deref,bool is_vertex_input,bool per_vertex)201 get_io_offset(nir_deref_instr *deref, bool is_vertex_input, bool per_vertex)
202 {
203    unsigned offset = 0;
204 
205    for (nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d)) {
206       if (d->deref_type == nir_deref_type_array) {
207          if (per_vertex && nir_deref_instr_parent(d)->deref_type == nir_deref_type_var)
208             break;
209 
210          if (!nir_src_is_const(d->arr.index))
211             return -1;
212 
213          offset += glsl_count_attribute_slots(d->type, is_vertex_input) *
214                    nir_src_as_uint(d->arr.index);
215       }
216       /* TODO: we can get the offset for structs here see nir_lower_io() */
217    }
218 
219    return offset;
220 }
221 
222 /**
223  * Try to mark a portion of the given varying as used.  Caller must ensure
224  * that the variable represents a shader input or output.
225  *
226  * If the index can't be interpreted as a constant, or some other problem
227  * occurs, then nothing will be marked and false will be returned.
228  */
229 static bool
try_mask_partial_io(nir_shader * shader,nir_variable * var,nir_deref_instr * deref,bool is_output_read)230 try_mask_partial_io(nir_shader *shader, nir_variable *var,
231                     nir_deref_instr *deref, bool is_output_read)
232 {
233    const struct glsl_type *type = var->type;
234    bool per_vertex = nir_is_per_vertex_io(var, shader->info.stage);
235 
236    if (per_vertex) {
237       assert(glsl_type_is_array(type));
238       type = glsl_get_array_element(type);
239    }
240 
241    /* Per view variables will be considered as a whole. */
242    if (var->data.per_view)
243       return false;
244 
245    /* The code below only handles:
246     *
247     * - Indexing into matrices
248     * - Indexing into arrays of (arrays, matrices, vectors, or scalars)
249     *
250     * For now, we just give up if we see varying structs and arrays of structs
251     * here marking the entire variable as used.
252     */
253    if (!(glsl_type_is_matrix(type) ||
254          (glsl_type_is_array(type) && !var->data.compact &&
255           (glsl_type_is_numeric(glsl_without_array(type)) ||
256            glsl_type_is_boolean(glsl_without_array(type)))))) {
257 
258       /* If we don't know how to handle this case, give up and let the
259        * caller mark the whole variable as used.
260        */
261       return false;
262    }
263 
264    unsigned offset = get_io_offset(deref, false, per_vertex);
265    if (offset == -1)
266       return false;
267 
268    unsigned num_elems;
269    unsigned elem_width = 1;
270    unsigned mat_cols = 1;
271    if (glsl_type_is_array(type)) {
272       num_elems = glsl_get_aoa_size(type);
273       if (glsl_type_is_matrix(glsl_without_array(type)))
274          mat_cols = glsl_get_matrix_columns(glsl_without_array(type));
275    } else {
276       num_elems = glsl_get_matrix_columns(type);
277    }
278 
279    /* double element width for double types that takes two slots */
280    if (glsl_type_is_dual_slot(glsl_without_array(type)))
281       elem_width *= 2;
282 
283    if (offset >= num_elems * elem_width * mat_cols) {
284       /* Constant index outside the bounds of the matrix/array.  This could
285        * arise as a result of constant folding of a legal GLSL program.
286        *
287        * Even though the spec says that indexing outside the bounds of a
288        * matrix/array results in undefined behaviour, we don't want to pass
289        * out-of-range values to set_io_mask() (since this could result in
290        * slots that don't exist being marked as used), so just let the caller
291        * mark the whole variable as used.
292        */
293       return false;
294    }
295 
296    set_io_mask(shader, var, offset, elem_width, deref, is_output_read);
297    return true;
298 }
299 
300 static void
update_memory_written_for_deref(nir_shader * shader,nir_deref_instr * deref)301 update_memory_written_for_deref(nir_shader *shader, nir_deref_instr *deref)
302 {
303    if (nir_deref_mode_may_be(deref, (nir_var_mem_ssbo | nir_var_mem_global)))
304       shader->info.writes_memory = true;
305 }
306 
307 static void
gather_intrinsic_info(nir_intrinsic_instr * instr,nir_shader * shader,void * dead_ctx)308 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
309                       void *dead_ctx)
310 {
311    uint64_t slot_mask = 0;
312 
313    if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
314       nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
315 
316       if (semantics.location >= VARYING_SLOT_PATCH0) {
317          /* Generic per-patch I/O. */
318          assert((shader->info.stage == MESA_SHADER_TESS_EVAL &&
319                  instr->intrinsic == nir_intrinsic_load_input) ||
320                 (shader->info.stage == MESA_SHADER_TESS_CTRL &&
321                  (instr->intrinsic == nir_intrinsic_load_output ||
322                   instr->intrinsic == nir_intrinsic_store_output)));
323 
324          semantics.location -= VARYING_SLOT_PATCH0;
325       }
326 
327       slot_mask = BITFIELD64_RANGE(semantics.location, semantics.num_slots);
328       assert(util_bitcount64(slot_mask) == semantics.num_slots);
329    }
330 
331    switch (instr->intrinsic) {
332    case nir_intrinsic_demote:
333    case nir_intrinsic_demote_if:
334       shader->info.fs.uses_demote = true;
335    /* fallthrough - quads with helper lanes only might be discarded entirely */
336    case nir_intrinsic_discard:
337    case nir_intrinsic_discard_if:
338       /* Freedreno uses the discard_if intrinsic to end GS invocations that
339        * don't produce a vertex, so we only set uses_discard if executing on
340        * a fragment shader. */
341       if (shader->info.stage == MESA_SHADER_FRAGMENT)
342          shader->info.fs.uses_discard = true;
343       break;
344 
345    case nir_intrinsic_terminate:
346    case nir_intrinsic_terminate_if:
347       assert(shader->info.stage == MESA_SHADER_FRAGMENT);
348       shader->info.fs.uses_discard = true;
349       break;
350 
351    case nir_intrinsic_interp_deref_at_centroid:
352    case nir_intrinsic_interp_deref_at_sample:
353    case nir_intrinsic_interp_deref_at_offset:
354    case nir_intrinsic_interp_deref_at_vertex:
355    case nir_intrinsic_load_deref:
356    case nir_intrinsic_store_deref:{
357       nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
358       if (nir_deref_mode_is_one_of(deref, nir_var_shader_in |
359                                           nir_var_shader_out)) {
360          nir_variable *var = nir_deref_instr_get_variable(deref);
361          bool is_output_read = false;
362          if (var->data.mode == nir_var_shader_out &&
363              instr->intrinsic == nir_intrinsic_load_deref)
364             is_output_read = true;
365 
366          if (!try_mask_partial_io(shader, var, deref, is_output_read))
367             mark_whole_variable(shader, var, deref, is_output_read);
368 
369          /* We need to track which input_reads bits correspond to a
370           * dvec3/dvec4 input attribute */
371          if (shader->info.stage == MESA_SHADER_VERTEX &&
372              var->data.mode == nir_var_shader_in &&
373              glsl_type_is_dual_slot(glsl_without_array(var->type))) {
374             for (unsigned i = 0; i < glsl_count_attribute_slots(var->type, false); i++) {
375                int idx = var->data.location + i;
376                shader->info.vs.double_inputs |= BITFIELD64_BIT(idx);
377             }
378          }
379       }
380       if (instr->intrinsic == nir_intrinsic_store_deref)
381          update_memory_written_for_deref(shader, deref);
382       break;
383    }
384 
385    case nir_intrinsic_load_input:
386    case nir_intrinsic_load_per_vertex_input:
387    case nir_intrinsic_load_input_vertex:
388    case nir_intrinsic_load_interpolated_input:
389       if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
390           instr->intrinsic == nir_intrinsic_load_input) {
391          shader->info.patch_inputs_read |= slot_mask;
392          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
393             shader->info.patch_inputs_read_indirectly |= slot_mask;
394       } else {
395          shader->info.inputs_read |= slot_mask;
396          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
397             shader->info.inputs_read_indirectly |= slot_mask;
398       }
399 
400       if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
401           instr->intrinsic == nir_intrinsic_load_per_vertex_input &&
402           !src_is_invocation_id(nir_get_io_vertex_index_src(instr)))
403          shader->info.tess.tcs_cross_invocation_inputs_read |= slot_mask;
404       break;
405 
406    case nir_intrinsic_load_output:
407    case nir_intrinsic_load_per_vertex_output:
408       if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
409           instr->intrinsic == nir_intrinsic_load_output) {
410          shader->info.patch_outputs_read |= slot_mask;
411          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
412             shader->info.patch_outputs_accessed_indirectly |= slot_mask;
413       } else {
414          shader->info.outputs_read |= slot_mask;
415          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
416             shader->info.outputs_accessed_indirectly |= slot_mask;
417       }
418 
419       if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
420           instr->intrinsic == nir_intrinsic_load_per_vertex_output &&
421           !src_is_invocation_id(nir_get_io_vertex_index_src(instr)))
422          shader->info.tess.tcs_cross_invocation_outputs_read |= slot_mask;
423 
424       if (shader->info.stage == MESA_SHADER_FRAGMENT &&
425           nir_intrinsic_io_semantics(instr).fb_fetch_output)
426          shader->info.fs.uses_fbfetch_output = true;
427       break;
428 
429    case nir_intrinsic_store_output:
430    case nir_intrinsic_store_per_vertex_output:
431       if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
432           instr->intrinsic == nir_intrinsic_store_output) {
433          shader->info.patch_outputs_written |= slot_mask;
434          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
435             shader->info.patch_outputs_accessed_indirectly |= slot_mask;
436       } else {
437          shader->info.outputs_written |= slot_mask;
438          if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
439             shader->info.outputs_accessed_indirectly |= slot_mask;
440       }
441 
442       if (shader->info.stage == MESA_SHADER_FRAGMENT &&
443           nir_intrinsic_io_semantics(instr).dual_source_blend_index)
444          shader->info.fs.color_is_dual_source = true;
445       break;
446 
447    case nir_intrinsic_load_color0:
448    case nir_intrinsic_load_color1:
449       shader->info.inputs_read |=
450          BITFIELD64_BIT(VARYING_SLOT_COL0 <<
451                         (instr->intrinsic == nir_intrinsic_load_color1));
452       /* fall through */
453    case nir_intrinsic_load_subgroup_size:
454    case nir_intrinsic_load_subgroup_invocation:
455    case nir_intrinsic_load_subgroup_eq_mask:
456    case nir_intrinsic_load_subgroup_ge_mask:
457    case nir_intrinsic_load_subgroup_gt_mask:
458    case nir_intrinsic_load_subgroup_le_mask:
459    case nir_intrinsic_load_subgroup_lt_mask:
460    case nir_intrinsic_load_num_subgroups:
461    case nir_intrinsic_load_subgroup_id:
462    case nir_intrinsic_load_vertex_id:
463    case nir_intrinsic_load_instance_id:
464    case nir_intrinsic_load_vertex_id_zero_base:
465    case nir_intrinsic_load_base_vertex:
466    case nir_intrinsic_load_first_vertex:
467    case nir_intrinsic_load_is_indexed_draw:
468    case nir_intrinsic_load_base_instance:
469    case nir_intrinsic_load_draw_id:
470    case nir_intrinsic_load_invocation_id:
471    case nir_intrinsic_load_frag_coord:
472    case nir_intrinsic_load_point_coord:
473    case nir_intrinsic_load_line_coord:
474    case nir_intrinsic_load_front_face:
475    case nir_intrinsic_load_sample_id:
476    case nir_intrinsic_load_sample_pos:
477    case nir_intrinsic_load_sample_mask_in:
478    case nir_intrinsic_load_helper_invocation:
479    case nir_intrinsic_load_tess_coord:
480    case nir_intrinsic_load_patch_vertices_in:
481    case nir_intrinsic_load_primitive_id:
482    case nir_intrinsic_load_tess_level_outer:
483    case nir_intrinsic_load_tess_level_inner:
484    case nir_intrinsic_load_tess_level_outer_default:
485    case nir_intrinsic_load_tess_level_inner_default:
486    case nir_intrinsic_load_local_invocation_id:
487    case nir_intrinsic_load_local_invocation_index:
488    case nir_intrinsic_load_global_invocation_id:
489    case nir_intrinsic_load_base_global_invocation_id:
490    case nir_intrinsic_load_global_invocation_index:
491    case nir_intrinsic_load_work_group_id:
492    case nir_intrinsic_load_num_work_groups:
493    case nir_intrinsic_load_local_group_size:
494    case nir_intrinsic_load_work_dim:
495    case nir_intrinsic_load_user_data_amd:
496    case nir_intrinsic_load_view_index:
497    case nir_intrinsic_load_barycentric_model:
498    case nir_intrinsic_load_gs_header_ir3:
499    case nir_intrinsic_load_tcs_header_ir3:
500       BITSET_SET(shader->info.system_values_read,
501                  nir_system_value_from_intrinsic(instr->intrinsic));
502       break;
503 
504    case nir_intrinsic_load_barycentric_pixel:
505       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
506           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
507          BITSET_SET(shader->info.system_values_read,
508                     SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
509       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
510          BITSET_SET(shader->info.system_values_read,
511                     SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
512       }
513       break;
514 
515    case nir_intrinsic_load_barycentric_centroid:
516       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
517           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
518          BITSET_SET(shader->info.system_values_read,
519                     SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
520       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
521          BITSET_SET(shader->info.system_values_read,
522                     SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
523       }
524       break;
525 
526    case nir_intrinsic_load_barycentric_sample:
527       if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
528           nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
529          BITSET_SET(shader->info.system_values_read,
530                     SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
531       } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
532          BITSET_SET(shader->info.system_values_read,
533                     SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
534       }
535       if (shader->info.stage == MESA_SHADER_FRAGMENT)
536          shader->info.fs.uses_sample_qualifier = true;
537       break;
538 
539    case nir_intrinsic_quad_broadcast:
540    case nir_intrinsic_quad_swap_horizontal:
541    case nir_intrinsic_quad_swap_vertical:
542    case nir_intrinsic_quad_swap_diagonal:
543       if (shader->info.stage == MESA_SHADER_FRAGMENT)
544          shader->info.fs.needs_helper_invocations = true;
545       break;
546 
547    case nir_intrinsic_end_primitive:
548    case nir_intrinsic_end_primitive_with_counter:
549       assert(shader->info.stage == MESA_SHADER_GEOMETRY);
550       shader->info.gs.uses_end_primitive = 1;
551       /* fall through */
552 
553    case nir_intrinsic_emit_vertex:
554    case nir_intrinsic_emit_vertex_with_counter:
555       shader->info.gs.active_stream_mask |= 1 << nir_intrinsic_stream_id(instr);
556 
557       break;
558 
559    case nir_intrinsic_atomic_counter_inc:
560    case nir_intrinsic_atomic_counter_inc_deref:
561    case nir_intrinsic_atomic_counter_add:
562    case nir_intrinsic_atomic_counter_add_deref:
563    case nir_intrinsic_atomic_counter_pre_dec:
564    case nir_intrinsic_atomic_counter_pre_dec_deref:
565    case nir_intrinsic_atomic_counter_post_dec:
566    case nir_intrinsic_atomic_counter_post_dec_deref:
567    case nir_intrinsic_atomic_counter_min:
568    case nir_intrinsic_atomic_counter_min_deref:
569    case nir_intrinsic_atomic_counter_max:
570    case nir_intrinsic_atomic_counter_max_deref:
571    case nir_intrinsic_atomic_counter_and:
572    case nir_intrinsic_atomic_counter_and_deref:
573    case nir_intrinsic_atomic_counter_or:
574    case nir_intrinsic_atomic_counter_or_deref:
575    case nir_intrinsic_atomic_counter_xor:
576    case nir_intrinsic_atomic_counter_xor_deref:
577    case nir_intrinsic_atomic_counter_exchange:
578    case nir_intrinsic_atomic_counter_exchange_deref:
579    case nir_intrinsic_atomic_counter_comp_swap:
580    case nir_intrinsic_atomic_counter_comp_swap_deref:
581    case nir_intrinsic_bindless_image_atomic_add:
582    case nir_intrinsic_bindless_image_atomic_and:
583    case nir_intrinsic_bindless_image_atomic_comp_swap:
584    case nir_intrinsic_bindless_image_atomic_dec_wrap:
585    case nir_intrinsic_bindless_image_atomic_exchange:
586    case nir_intrinsic_bindless_image_atomic_fadd:
587    case nir_intrinsic_bindless_image_atomic_imax:
588    case nir_intrinsic_bindless_image_atomic_imin:
589    case nir_intrinsic_bindless_image_atomic_inc_wrap:
590    case nir_intrinsic_bindless_image_atomic_or:
591    case nir_intrinsic_bindless_image_atomic_umax:
592    case nir_intrinsic_bindless_image_atomic_umin:
593    case nir_intrinsic_bindless_image_atomic_xor:
594    case nir_intrinsic_bindless_image_store:
595    case nir_intrinsic_bindless_image_store_raw_intel:
596    case nir_intrinsic_global_atomic_add:
597    case nir_intrinsic_global_atomic_and:
598    case nir_intrinsic_global_atomic_comp_swap:
599    case nir_intrinsic_global_atomic_exchange:
600    case nir_intrinsic_global_atomic_fadd:
601    case nir_intrinsic_global_atomic_fcomp_swap:
602    case nir_intrinsic_global_atomic_fmax:
603    case nir_intrinsic_global_atomic_fmin:
604    case nir_intrinsic_global_atomic_imax:
605    case nir_intrinsic_global_atomic_imin:
606    case nir_intrinsic_global_atomic_or:
607    case nir_intrinsic_global_atomic_umax:
608    case nir_intrinsic_global_atomic_umin:
609    case nir_intrinsic_global_atomic_xor:
610    case nir_intrinsic_image_atomic_add:
611    case nir_intrinsic_image_atomic_and:
612    case nir_intrinsic_image_atomic_comp_swap:
613    case nir_intrinsic_image_atomic_dec_wrap:
614    case nir_intrinsic_image_atomic_exchange:
615    case nir_intrinsic_image_atomic_fadd:
616    case nir_intrinsic_image_atomic_imax:
617    case nir_intrinsic_image_atomic_imin:
618    case nir_intrinsic_image_atomic_inc_wrap:
619    case nir_intrinsic_image_atomic_or:
620    case nir_intrinsic_image_atomic_umax:
621    case nir_intrinsic_image_atomic_umin:
622    case nir_intrinsic_image_atomic_xor:
623    case nir_intrinsic_image_deref_atomic_add:
624    case nir_intrinsic_image_deref_atomic_and:
625    case nir_intrinsic_image_deref_atomic_comp_swap:
626    case nir_intrinsic_image_deref_atomic_dec_wrap:
627    case nir_intrinsic_image_deref_atomic_exchange:
628    case nir_intrinsic_image_deref_atomic_fadd:
629    case nir_intrinsic_image_deref_atomic_imax:
630    case nir_intrinsic_image_deref_atomic_imin:
631    case nir_intrinsic_image_deref_atomic_inc_wrap:
632    case nir_intrinsic_image_deref_atomic_or:
633    case nir_intrinsic_image_deref_atomic_umax:
634    case nir_intrinsic_image_deref_atomic_umin:
635    case nir_intrinsic_image_deref_atomic_xor:
636    case nir_intrinsic_image_deref_store:
637    case nir_intrinsic_image_deref_store_raw_intel:
638    case nir_intrinsic_image_store:
639    case nir_intrinsic_image_store_raw_intel:
640    case nir_intrinsic_ssbo_atomic_add:
641    case nir_intrinsic_ssbo_atomic_add_ir3:
642    case nir_intrinsic_ssbo_atomic_and:
643    case nir_intrinsic_ssbo_atomic_and_ir3:
644    case nir_intrinsic_ssbo_atomic_comp_swap:
645    case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
646    case nir_intrinsic_ssbo_atomic_exchange:
647    case nir_intrinsic_ssbo_atomic_exchange_ir3:
648    case nir_intrinsic_ssbo_atomic_fadd:
649    case nir_intrinsic_ssbo_atomic_fcomp_swap:
650    case nir_intrinsic_ssbo_atomic_fmax:
651    case nir_intrinsic_ssbo_atomic_fmin:
652    case nir_intrinsic_ssbo_atomic_imax:
653    case nir_intrinsic_ssbo_atomic_imax_ir3:
654    case nir_intrinsic_ssbo_atomic_imin:
655    case nir_intrinsic_ssbo_atomic_imin_ir3:
656    case nir_intrinsic_ssbo_atomic_or:
657    case nir_intrinsic_ssbo_atomic_or_ir3:
658    case nir_intrinsic_ssbo_atomic_umax:
659    case nir_intrinsic_ssbo_atomic_umax_ir3:
660    case nir_intrinsic_ssbo_atomic_umin:
661    case nir_intrinsic_ssbo_atomic_umin_ir3:
662    case nir_intrinsic_ssbo_atomic_xor:
663    case nir_intrinsic_ssbo_atomic_xor_ir3:
664    case nir_intrinsic_store_global:
665    case nir_intrinsic_store_global_ir3:
666    case nir_intrinsic_store_ssbo:
667    case nir_intrinsic_store_ssbo_ir3:
668       /* Only set this for globally visible memory, not scratch and not
669        * shared.
670        */
671       shader->info.writes_memory = true;
672       break;
673 
674    case nir_intrinsic_deref_atomic_add:
675    case nir_intrinsic_deref_atomic_imin:
676    case nir_intrinsic_deref_atomic_umin:
677    case nir_intrinsic_deref_atomic_imax:
678    case nir_intrinsic_deref_atomic_umax:
679    case nir_intrinsic_deref_atomic_and:
680    case nir_intrinsic_deref_atomic_or:
681    case nir_intrinsic_deref_atomic_xor:
682    case nir_intrinsic_deref_atomic_exchange:
683    case nir_intrinsic_deref_atomic_comp_swap:
684       update_memory_written_for_deref(shader, nir_src_as_deref(instr->src[0]));
685       break;
686 
687    default:
688       break;
689    }
690 }
691 
692 static void
gather_tex_info(nir_tex_instr * instr,nir_shader * shader)693 gather_tex_info(nir_tex_instr *instr, nir_shader *shader)
694 {
695    if (shader->info.stage == MESA_SHADER_FRAGMENT &&
696        nir_tex_instr_has_implicit_derivative(instr))
697       shader->info.fs.needs_helper_invocations = true;
698 
699    switch (instr->op) {
700    case nir_texop_tg4:
701       shader->info.uses_texture_gather = true;
702       break;
703    default:
704       break;
705    }
706 }
707 
708 static void
gather_alu_info(nir_alu_instr * instr,nir_shader * shader)709 gather_alu_info(nir_alu_instr *instr, nir_shader *shader)
710 {
711    switch (instr->op) {
712    case nir_op_fddx:
713    case nir_op_fddy:
714       shader->info.uses_fddx_fddy = true;
715       /* Fall through */
716    case nir_op_fddx_fine:
717    case nir_op_fddy_fine:
718    case nir_op_fddx_coarse:
719    case nir_op_fddy_coarse:
720       if (shader->info.stage == MESA_SHADER_FRAGMENT)
721          shader->info.fs.needs_helper_invocations = true;
722       break;
723    default:
724       break;
725    }
726 
727    const nir_op_info *info = &nir_op_infos[instr->op];
728 
729    for (unsigned i = 0; i < info->num_inputs; i++) {
730       if (nir_alu_type_get_base_type(info->input_types[i]) == nir_type_float)
731          shader->info.bit_sizes_float |= nir_src_bit_size(instr->src[i].src);
732       else
733          shader->info.bit_sizes_int |= nir_src_bit_size(instr->src[i].src);
734    }
735    if (nir_alu_type_get_base_type(info->output_type) == nir_type_float)
736       shader->info.bit_sizes_float |= nir_dest_bit_size(instr->dest.dest);
737    else
738       shader->info.bit_sizes_int |= nir_dest_bit_size(instr->dest.dest);
739 }
740 
741 static void
gather_info_block(nir_block * block,nir_shader * shader,void * dead_ctx)742 gather_info_block(nir_block *block, nir_shader *shader, void *dead_ctx)
743 {
744    nir_foreach_instr(instr, block) {
745       switch (instr->type) {
746       case nir_instr_type_alu:
747          gather_alu_info(nir_instr_as_alu(instr), shader);
748          break;
749       case nir_instr_type_intrinsic:
750          gather_intrinsic_info(nir_instr_as_intrinsic(instr), shader, dead_ctx);
751          break;
752       case nir_instr_type_tex:
753          gather_tex_info(nir_instr_as_tex(instr), shader);
754          break;
755       case nir_instr_type_call:
756          assert(!"nir_shader_gather_info only works if functions are inlined");
757          break;
758       default:
759          break;
760       }
761    }
762 }
763 
764 void
nir_shader_gather_info(nir_shader * shader,nir_function_impl * entrypoint)765 nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
766 {
767    shader->info.num_textures = 0;
768    shader->info.num_images = 0;
769    shader->info.image_buffers = 0;
770    shader->info.msaa_images = 0;
771    shader->info.bit_sizes_float = 0;
772    shader->info.bit_sizes_int = 0;
773 
774    nir_foreach_uniform_variable(var, shader) {
775       /* Bindless textures and images don't use non-bindless slots.
776        * Interface blocks imply inputs, outputs, UBO, or SSBO, which can only
777        * mean bindless.
778        */
779       if (var->data.bindless || var->interface_type)
780          continue;
781 
782       shader->info.num_textures += glsl_type_get_sampler_count(var->type);
783 
784       unsigned num_image_slots = glsl_type_get_image_count(var->type);
785       if (num_image_slots) {
786          const struct glsl_type *image_type = glsl_without_array(var->type);
787 
788          if (glsl_get_sampler_dim(image_type) == GLSL_SAMPLER_DIM_BUF) {
789             shader->info.image_buffers |=
790                BITFIELD_RANGE(shader->info.num_images, num_image_slots);
791          }
792          if (glsl_get_sampler_dim(image_type) == GLSL_SAMPLER_DIM_MS) {
793             shader->info.msaa_images |=
794                BITFIELD_RANGE(shader->info.num_images, num_image_slots);
795          }
796          shader->info.num_images += num_image_slots;
797       }
798    }
799 
800    shader->info.inputs_read = 0;
801    shader->info.outputs_written = 0;
802    shader->info.outputs_read = 0;
803    shader->info.patch_outputs_read = 0;
804    shader->info.patch_inputs_read = 0;
805    shader->info.patch_outputs_written = 0;
806    BITSET_ZERO(shader->info.system_values_read);
807    shader->info.inputs_read_indirectly = 0;
808    shader->info.outputs_accessed_indirectly = 0;
809    shader->info.patch_inputs_read_indirectly = 0;
810    shader->info.patch_outputs_accessed_indirectly = 0;
811 
812    if (shader->info.stage == MESA_SHADER_VERTEX) {
813       shader->info.vs.double_inputs = 0;
814    }
815    if (shader->info.stage == MESA_SHADER_FRAGMENT) {
816       shader->info.fs.uses_sample_qualifier = false;
817       shader->info.fs.uses_discard = false;
818       shader->info.fs.uses_demote = false;
819       shader->info.fs.color_is_dual_source = false;
820       shader->info.fs.uses_fbfetch_output = false;
821       shader->info.fs.needs_helper_invocations = false;
822    }
823    if (shader->info.stage == MESA_SHADER_TESS_CTRL) {
824       shader->info.tess.tcs_cross_invocation_inputs_read = 0;
825       shader->info.tess.tcs_cross_invocation_outputs_read = 0;
826    }
827 
828    shader->info.writes_memory = shader->info.has_transform_feedback_varyings;
829 
830    void *dead_ctx = ralloc_context(NULL);
831    nir_foreach_block(block, entrypoint) {
832       gather_info_block(block, shader, dead_ctx);
833    }
834    ralloc_free(dead_ctx);
835 }
836