1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "nir.h"
25
26 static bool
assert_ssa_def_is_not_1bit(nir_ssa_def * def,UNUSED void * unused)27 assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
28 {
29 assert(def->bit_size > 1);
30 return true;
31 }
32
33 static bool
rewrite_1bit_ssa_def_to_32bit(nir_ssa_def * def,void * _progress)34 rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
35 {
36 bool *progress = _progress;
37 if (def->bit_size == 1) {
38 def->bit_size = 32;
39 *progress = true;
40 }
41 return true;
42 }
43
44 static bool
lower_alu_instr(nir_alu_instr * alu)45 lower_alu_instr(nir_alu_instr *alu)
46 {
47 const nir_op_info *op_info = &nir_op_infos[alu->op];
48
49 assert(alu->dest.dest.is_ssa);
50
51 switch (alu->op) {
52 case nir_op_mov:
53 case nir_op_vec2:
54 case nir_op_vec3:
55 case nir_op_vec4:
56 case nir_op_vec8:
57 case nir_op_vec16:
58 case nir_op_inot:
59 case nir_op_iand:
60 case nir_op_ior:
61 case nir_op_ixor:
62 if (alu->dest.dest.ssa.bit_size != 1)
63 return false;
64 /* These we expect to have booleans but the opcode doesn't change */
65 break;
66
67 case nir_op_f2b1: alu->op = nir_op_f2b32; break;
68 case nir_op_i2b1: alu->op = nir_op_i2b32; break;
69
70 case nir_op_b2b32:
71 case nir_op_b2b1:
72 /* We're mutating instructions in a dominance-preserving order so our
73 * source boolean should be 32-bit by now.
74 */
75 assert(nir_src_bit_size(alu->src[0].src) == 32);
76 alu->op = nir_op_mov;
77 break;
78
79 case nir_op_flt: alu->op = nir_op_flt32; break;
80 case nir_op_fge: alu->op = nir_op_fge32; break;
81 case nir_op_feq: alu->op = nir_op_feq32; break;
82 case nir_op_fneu: alu->op = nir_op_fneu32; break;
83 case nir_op_ilt: alu->op = nir_op_ilt32; break;
84 case nir_op_ige: alu->op = nir_op_ige32; break;
85 case nir_op_ieq: alu->op = nir_op_ieq32; break;
86 case nir_op_ine: alu->op = nir_op_ine32; break;
87 case nir_op_ult: alu->op = nir_op_ult32; break;
88 case nir_op_uge: alu->op = nir_op_uge32; break;
89
90 case nir_op_ball_fequal2: alu->op = nir_op_b32all_fequal2; break;
91 case nir_op_ball_fequal3: alu->op = nir_op_b32all_fequal3; break;
92 case nir_op_ball_fequal4: alu->op = nir_op_b32all_fequal4; break;
93 case nir_op_bany_fnequal2: alu->op = nir_op_b32any_fnequal2; break;
94 case nir_op_bany_fnequal3: alu->op = nir_op_b32any_fnequal3; break;
95 case nir_op_bany_fnequal4: alu->op = nir_op_b32any_fnequal4; break;
96 case nir_op_ball_iequal2: alu->op = nir_op_b32all_iequal2; break;
97 case nir_op_ball_iequal3: alu->op = nir_op_b32all_iequal3; break;
98 case nir_op_ball_iequal4: alu->op = nir_op_b32all_iequal4; break;
99 case nir_op_bany_inequal2: alu->op = nir_op_b32any_inequal2; break;
100 case nir_op_bany_inequal3: alu->op = nir_op_b32any_inequal3; break;
101 case nir_op_bany_inequal4: alu->op = nir_op_b32any_inequal4; break;
102
103 case nir_op_bcsel: alu->op = nir_op_b32csel; break;
104
105 default:
106 assert(alu->dest.dest.ssa.bit_size > 1);
107 for (unsigned i = 0; i < op_info->num_inputs; i++)
108 assert(alu->src[i].src.ssa->bit_size > 1);
109 return false;
110 }
111
112 if (alu->dest.dest.ssa.bit_size == 1)
113 alu->dest.dest.ssa.bit_size = 32;
114
115 return true;
116 }
117
118 static bool
nir_lower_bool_to_int32_impl(nir_function_impl * impl)119 nir_lower_bool_to_int32_impl(nir_function_impl *impl)
120 {
121 bool progress = false;
122
123 nir_foreach_block(block, impl) {
124 nir_foreach_instr_safe(instr, block) {
125 switch (instr->type) {
126 case nir_instr_type_alu:
127 progress |= lower_alu_instr(nir_instr_as_alu(instr));
128 break;
129
130 case nir_instr_type_load_const: {
131 nir_load_const_instr *load = nir_instr_as_load_const(instr);
132 if (load->def.bit_size == 1) {
133 nir_const_value *value = load->value;
134 for (unsigned i = 0; i < load->def.num_components; i++)
135 load->value[i].u32 = value[i].b ? NIR_TRUE : NIR_FALSE;
136 load->def.bit_size = 32;
137 progress = true;
138 }
139 break;
140 }
141
142 case nir_instr_type_intrinsic:
143 case nir_instr_type_ssa_undef:
144 case nir_instr_type_phi:
145 case nir_instr_type_tex:
146 nir_foreach_ssa_def(instr, rewrite_1bit_ssa_def_to_32bit,
147 &progress);
148 break;
149
150 default:
151 nir_foreach_ssa_def(instr, assert_ssa_def_is_not_1bit, NULL);
152 }
153 }
154 }
155
156 if (progress) {
157 nir_metadata_preserve(impl, nir_metadata_block_index |
158 nir_metadata_dominance);
159 } else {
160 nir_metadata_preserve(impl, nir_metadata_all);
161 }
162
163 return progress;
164 }
165
166 bool
nir_lower_bool_to_int32(nir_shader * shader)167 nir_lower_bool_to_int32(nir_shader *shader)
168 {
169 bool progress = false;
170
171 nir_foreach_function(function, shader) {
172 if (function->impl && nir_lower_bool_to_int32_impl(function->impl))
173 progress = true;
174 }
175
176 return progress;
177 }
178