1#
2# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8include lib/libfdt/libfdt.mk
9include drivers/arm/gic/v2/gicv2.mk
10
11AW_PLAT			:=	plat/allwinner
12
13PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/aarch64	\
14				-I${AW_PLAT}/common/include		\
15				-I${AW_PLAT}/${PLAT}/include
16
17PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/${ARCH}/16550_console.S	\
18				${XLAT_TABLES_LIB_SRCS}			\
19				${AW_PLAT}/common/plat_helpers.S	\
20				${AW_PLAT}/common/sunxi_common.c
21
22BL31_SOURCES		+=	drivers/allwinner/axp/common.c		\
23				drivers/allwinner/sunxi_msgbox.c	\
24				drivers/arm/css/scpi/css_scpi.c		\
25				${GICV2_SOURCES}			\
26				drivers/delay_timer/delay_timer.c	\
27				drivers/delay_timer/generic_delay_timer.c \
28				lib/cpus/${ARCH}/cortex_a53.S		\
29				plat/common/plat_gicv2.c		\
30				plat/common/plat_psci_common.c		\
31				${AW_PLAT}/common/sunxi_bl31_setup.c	\
32				${AW_PLAT}/common/sunxi_cpu_ops.c	\
33				${AW_PLAT}/common/sunxi_pm.c		\
34				${AW_PLAT}/${PLAT}/sunxi_power.c	\
35				${AW_PLAT}/common/sunxi_security.c	\
36				${AW_PLAT}/common/sunxi_topology.c
37
38# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
39COLD_BOOT_SINGLE_CPU		:=	1
40
41# Do not enable SPE (not supported on ARM v8.0).
42ENABLE_SPE_FOR_LOWER_ELS	:=	0
43
44# Do not enable SVE (not supported on ARM v8.0).
45ENABLE_SVE_FOR_NS		:=	0
46
47# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
48ERRATA_A53_835769		:=	1
49ERRATA_A53_843419		:=	1
50ERRATA_A53_855873		:=	1
51ERRATA_A53_1530924		:=	1
52
53# The traditional U-Boot load address is 160MB into DRAM.
54PRELOADED_BL33_BASE		?=	0x4a000000
55
56# The reset vector can be changed for each CPU.
57PROGRAMMABLE_RESET_ADDRESS	:=	1
58
59# Allow mapping read-only data as execute-never.
60SEPARATE_CODE_AND_RODATA	:=	1
61
62# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
63SEPARATE_NOBITS_REGION		:=	1
64
65# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
66RESET_TO_BL31			:=	1
67
68# This platform is single-cluster and does not require coherency setup.
69WARMBOOT_ENABLE_DCACHE_EARLY	:=	1
70