1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/cci.h>
17 #include <drivers/console.h>
18 #include <lib/el3_runtime/context_mgmt.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables.h>
21 #include <plat/common/platform.h>
22
23 #include <imx8qx_pads.h>
24 #include <imx8_iomux.h>
25 #include <imx8_lpuart.h>
26 #include <plat_imx8.h>
27 #include <sci/sci.h>
28 #include <sec_rsrc.h>
29
30 static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
31 static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
32 static const unsigned long BL31_RO_START = BL_CODE_BASE;
33 static const unsigned long BL31_RO_END = BL_CODE_END;
34 static const unsigned long BL31_RW_END = BL_END;
35
36 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
37
38 static entry_point_info_t bl32_image_ep_info;
39 static entry_point_info_t bl33_image_ep_info;
40
41 /* Default configuration for i.MX8QM/QXP MEK */
42 #if defined(IMX_USE_UART0)
43 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
44 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
45 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
46 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
47 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
48 #define IMX_RES_UART SC_R_UART_0
49 #define IMX_PAD_UART_RX SC_P_UART0_RX
50 #define IMX_PAD_UART_TX SC_P_UART0_TX
51
52 /*
53 * On Toradex Colibri i.MX8QXP UART3 on the FLEXCAN2.
54 * Use custom pad control for this
55 */
56 #elif defined(IMX_USE_UART3)
57 /*
58 * FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX,
59 * For ref:
60 * 000b - ADMA_FLEXCAN2_RX
61 * 001b - ADMA_SAI3_RXD
62 * 010b - ADMA_UART3_RX
63 * 011b - ADMA_SAI1_RXFS
64 * 100b - LSIO_GPIO1_IO19
65 */
66 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
67 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
68 (2U << PADRING_IFMUX_SHIFT) | \
69 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
70 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
71 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
72 #define IMX_RES_UART SC_R_UART_3
73 #define IMX_PAD_UART_RX SC_P_FLEXCAN2_RX
74 #define IMX_PAD_UART_TX SC_P_FLEXCAN2_TX
75 #else
76 #error "Provide proper UART configuration in IMX_DEBUG_UART"
77 #endif
78
79 static const mmap_region_t imx_mmap[] = {
80 MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW),
81 {0}
82 };
83
get_spsr_for_bl33_entry(void)84 static uint32_t get_spsr_for_bl33_entry(void)
85 {
86 unsigned long el_status;
87 unsigned long mode;
88 uint32_t spsr;
89
90 /* figure out what mode we enter the non-secure world */
91 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
92 el_status &= ID_AA64PFR0_ELX_MASK;
93
94 mode = (el_status) ? MODE_EL2 : MODE_EL1;
95
96 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
97 return spsr;
98 }
99
100 #if DEBUG_CONSOLE_A35
lpuart32_serial_setbrg(unsigned int base,int baudrate)101 static void lpuart32_serial_setbrg(unsigned int base, int baudrate)
102 {
103 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr;
104 unsigned int diff1, diff2, tmp, rate;
105
106 if (baudrate == 0)
107 panic();
108
109 sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
110
111 baud_diff = baudrate;
112 osr = 0;
113 sbr = 0;
114 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
115 tmp_sbr = (rate / (baudrate * tmp_osr));
116 if (tmp_sbr == 0)
117 tmp_sbr = 1;
118
119 /* calculate difference in actual baud w/ current values */
120 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate;
121 diff2 = rate / (tmp_osr * (tmp_sbr + 1));
122
123 /* select best values between sbr and sbr+1 */
124 if (diff1 > (baudrate - diff2)) {
125 diff1 = baudrate - diff2;
126 tmp_sbr++;
127 }
128
129 if (diff1 <= baud_diff) {
130 baud_diff = diff1;
131 osr = tmp_osr;
132 sbr = tmp_sbr;
133 }
134 }
135
136 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD);
137
138 if ((osr > 3) && (osr < 8))
139 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
140
141 tmp &= ~LPUART_BAUD_OSR_MASK;
142 tmp |= LPUART_BAUD_OSR(osr - 1);
143 tmp &= ~LPUART_BAUD_SBR_MASK;
144 tmp |= LPUART_BAUD_SBR(sbr);
145
146 /* explicitly disable 10 bit mode & set 1 stop bit */
147 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
148
149 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp);
150 }
151
lpuart32_serial_init(unsigned int base)152 static int lpuart32_serial_init(unsigned int base)
153 {
154 unsigned int tmp;
155
156 /* disable TX & RX before enabling clocks */
157 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
158 tmp &= ~(CTRL_TE | CTRL_RE);
159 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
160
161 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0);
162 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE));
163
164 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0);
165
166 /* provide data bits, parity, stop bit, etc */
167 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE);
168
169 /* eight data bits no parity bit */
170 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
171 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
172 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
173
174 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE);
175
176 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
177 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
178 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A);
179
180 return 0;
181 }
182 #endif
183
imx8_partition_resources(void)184 void imx8_partition_resources(void)
185 {
186 sc_rm_pt_t secure_part, os_part;
187 sc_rm_mr_t mr, mr_record = 64;
188 sc_faddr_t start, end;
189 sc_err_t err;
190 bool owned;
191 int i;
192
193 err = sc_rm_get_partition(ipc_handle, &secure_part);
194 if (err)
195 ERROR("sc_rm_get_partition failed: %u\n", err);
196
197 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,
198 false, false, false);
199 if (err)
200 ERROR("sc_rm_partition_alloc failed: %u\n", err);
201
202 err = sc_rm_set_parent(ipc_handle, os_part, secure_part);
203 if (err)
204 ERROR("sc_rm_set_parent: %u\n", err);
205
206 /* set secure resources to NOT-movable */
207 for (i = 0; i < (ARRAY_SIZE(secure_rsrcs)); i++) {
208 err = sc_rm_set_resource_movable(ipc_handle,
209 secure_rsrcs[i], secure_rsrcs[i], false);
210 if (err)
211 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
212 secure_rsrcs[i], err);
213 }
214
215 /* move all movable resources and pins to non-secure partition */
216 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);
217 if (err)
218 ERROR("sc_rm_move_all: %u\n", err);
219
220 /* iterate through peripherals to give NS OS part access */
221 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) {
222 err = sc_rm_set_peripheral_permissions(ipc_handle,
223 ns_access_allowed[i], os_part, SC_RM_PERM_FULL);
224 if (err)
225 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \
226 ret %u\n", ns_access_allowed[i], err);
227 }
228
229 /*
230 * sc_rm_set_peripheral_permissions
231 * sc_rm_set_memreg_permissions
232 * sc_rm_set_pin_movable
233 */
234 for (mr = 0; mr < 64; mr++) {
235 owned = sc_rm_is_memreg_owned(ipc_handle, mr);
236 if (owned) {
237 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
238 if (err)
239 ERROR("Memreg get info failed, %u\n", mr);
240
241 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
242 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
243 mr_record = mr; /* Record the mr for ATF running */
244 } else {
245 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
246 if (err)
247 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
248 err %d\n", start, end, err);
249 }
250 }
251 }
252
253 if (mr_record != 64) {
254 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);
255 if (err)
256 ERROR("Memreg get info failed, %u\n", mr_record);
257 if ((BL31_LIMIT - 1) < end) {
258 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
259 if (err)
260 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
261 (sc_faddr_t)BL31_LIMIT, end);
262 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
263 if (err)
264 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
265 (sc_faddr_t)BL31_LIMIT, end);
266 }
267
268 if (start < (BL31_BASE - 1)) {
269 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
270 if (err)
271 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
272 start, (sc_faddr_t)BL31_BASE - 1);
273 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
274 if (err)
275 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
276 start, (sc_faddr_t)BL31_BASE - 1);
277 }
278 }
279
280 if (err)
281 NOTICE("Partitioning Failed\n");
282 else
283 NOTICE("Non-secure Partitioning Succeeded\n");
284 }
285
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)286 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
287 u_register_t arg2, u_register_t arg3)
288 {
289 #if DEBUG_CONSOLE
290 static console_t console;
291 #endif
292 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
293 panic();
294
295 #if DEBUG_CONSOLE_A35
296 sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART,
297 SC_PM_PW_MODE_ON);
298 sc_pm_clock_rate_t rate = 80000000;
299 sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
300 sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false);
301
302 /* Configure UART pads */
303 sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL);
304 sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL);
305 lpuart32_serial_init(IMX_BOOT_UART_BASE);
306 #endif
307
308 #if DEBUG_CONSOLE
309 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
310 IMX_CONSOLE_BAUDRATE, &console);
311 #endif
312 /* Turn on MU1 for non-secure OS/Hypervisor */
313 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
314
315 /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
316 sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
317 sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
318 mmio_write_32(IMX_GPT0_LPCG_BASE, mmio_read_32(IMX_GPT0_LPCG_BASE) | (1 << 25));
319
320 /*
321 * create new partition for non-secure OS/Hypervisor
322 * uses global structs defined in sec_rsrc.h
323 */
324 imx8_partition_resources();
325
326 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
327 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
328 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
329 }
330
bl31_plat_arch_setup(void)331 void bl31_plat_arch_setup(void)
332 {
333 unsigned long ro_start = BL31_RO_START;
334 unsigned long ro_size = BL31_RO_END - BL31_RO_START;
335 unsigned long rw_start = BL31_RW_START;
336 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
337 #if USE_COHERENT_MEM
338 unsigned long coh_start = BL31_COHERENT_RAM_START;
339 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START;
340 #endif
341
342 mmap_add_region(ro_start, ro_start, ro_size,
343 MT_RO | MT_MEMORY | MT_SECURE);
344 mmap_add_region(rw_start, rw_start, rw_size,
345 MT_RW | MT_MEMORY | MT_SECURE);
346 mmap_add(imx_mmap);
347
348 #if USE_COHERENT_MEM
349 mmap_add_region(coh_start, coh_start, coh_size,
350 MT_DEVICE | MT_RW | MT_SECURE);
351 #endif
352
353 init_xlat_tables();
354 enable_mmu_el3(0);
355 }
356
bl31_platform_setup(void)357 void bl31_platform_setup(void)
358 {
359 plat_gic_driver_init();
360 plat_gic_init();
361 }
362
bl31_plat_get_next_image_ep_info(unsigned int type)363 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
364 {
365 if (type == NON_SECURE)
366 return &bl33_image_ep_info;
367 if (type == SECURE)
368 return &bl32_image_ep_info;
369
370 return NULL;
371 }
372
plat_get_syscnt_freq2(void)373 unsigned int plat_get_syscnt_freq2(void)
374 {
375 return COUNTER_FREQUENCY;
376 }
377
bl31_plat_runtime_setup(void)378 void bl31_plat_runtime_setup(void)
379 {
380 return;
381 }
382