1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_asm.h"
24 #include "r700_sq.h"
25
r700_bytecode_cf_vtx_build(uint32_t * bytecode,const struct r600_bytecode_cf * cf)26 void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
27 {
28 unsigned count = (cf->ndw / 4) - 1;
29 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
30 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
31 S_SQ_CF_WORD1_BARRIER(1) |
32 S_SQ_CF_WORD1_COUNT(count) |
33 S_SQ_CF_WORD1_COUNT_3(count >> 3)|
34 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
35 }
36
r700_bytecode_alu_build(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,unsigned id)37 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
38 {
39 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
40 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
41 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
42 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
43 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
44 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
45 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
46 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
47 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
48 S_SQ_ALU_WORD0_LAST(alu->last);
49
50 /* don't replace gpr by pv or ps for destination register */
51 if (alu->is_op3) {
52 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
53 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
54 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
55 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
56 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
57 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
58 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
59 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
60 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
61 S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
62 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
63 } else {
64 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
65 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
66 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
67 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
68 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
69 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
70 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
71 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
72 S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
73 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
74 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
75 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
76 }
77 return 0;
78 }
79
r700_bytecode_alu_read(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,uint32_t word0,uint32_t word1)80 void r700_bytecode_alu_read(struct r600_bytecode *bc,
81 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
82 {
83 /* WORD0 */
84 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
85 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
86 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
87 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
88 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
89 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
90 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
91 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
92 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
93 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
94 alu->last = G_SQ_ALU_WORD0_LAST(word0);
95
96 /* WORD1 */
97 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
98 if (alu->bank_swizzle)
99 alu->bank_swizzle_force = alu->bank_swizzle;
100 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
101 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
102 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
103 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
104 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
105 {
106 alu->is_op3 = 1;
107 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
108 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
109 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
110 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
111 alu->op = r600_isa_alu_by_opcode(bc->isa,
112 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1);
113 }
114 else /*ALU_DWORD1_OP2*/
115 {
116 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
117 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
118 alu->op = r600_isa_alu_by_opcode(bc->isa,
119 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0);
120 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
121 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
122 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
123 alu->execute_mask =
124 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
125 }
126 }
127
r700_bytecode_fetch_mem_build(struct r600_bytecode * bc,struct r600_bytecode_vtx * mem,unsigned id)128 int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *mem, unsigned id)
129 {
130 unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8;
131
132 bc->bytecode[id++] = S_SQ_MEM_RD_WORD0_MEM_INST(2) |
133 S_SQ_MEM_RD_WORD0_ELEM_SIZE(mem->elem_size) |
134 S_SQ_MEM_RD_WORD0_FETCH_WHOLE_QUAD(0) |
135 S_SQ_MEM_RD_WORD0_MEM_OP(opcode) |
136 S_SQ_MEM_RD_WORD0_UNCACHED(mem->uncached) |
137 S_SQ_MEM_RD_WORD0_INDEXED(mem->indexed) |
138 S_SQ_MEM_RD_WORD0_SRC_SEL_Y(mem->src_sel_y) |
139 S_SQ_MEM_RD_WORD0_SRC_GPR(mem->src_gpr) |
140 S_SQ_MEM_RD_WORD0_SRC_REL(mem->src_rel) |
141 S_SQ_MEM_RD_WORD0_SRC_SEL_X(mem->src_sel_x) |
142 S_SQ_MEM_RD_WORD0_BURST_COUNT(mem->burst_count) |
143 S_SQ_MEM_RD_WORD0_LDS_REQ(0) |
144 S_SQ_MEM_RD_WORD0_COALESCED_READ(0);
145
146 bc->bytecode[id++] = S_SQ_MEM_RD_WORD1_DST_GPR(mem->dst_gpr) |
147 S_SQ_MEM_RD_WORD1_DST_REL(mem->dst_rel) |
148 S_SQ_MEM_RD_WORD1_DST_SEL_X(mem->dst_sel_x) |
149 S_SQ_MEM_RD_WORD1_DST_SEL_Y(mem->dst_sel_y) |
150 S_SQ_MEM_RD_WORD1_DST_SEL_W(mem->dst_sel_w) |
151 S_SQ_MEM_RD_WORD1_DST_SEL_Z(mem->dst_sel_z) |
152 S_SQ_MEM_RD_WORD1_DATA_FORMAT(mem->data_format) |
153 S_SQ_MEM_RD_WORD1_NUM_FORMAT_ALL(mem->num_format_all) |
154 S_SQ_MEM_RD_WORD1_FORMAT_COMP_ALL(mem->format_comp_all) |
155 S_SQ_MEM_RD_WORD1_SRF_MODE_ALL(mem->srf_mode_all);
156
157 bc->bytecode[id++] = S_SQ_MEM_RD_WORD2_ARRAY_BASE(mem->array_base) |
158 S_SQ_MEM_RD_WORD2_ENDIAN_SWAP(0) |
159 S_SQ_MEM_RD_WORD2_ARRAY_SIZE(mem->array_size);
160
161
162 bc->bytecode[id++] = 0; /* MEM ops are 4 word aligned */
163
164 return 0;
165 }
166