1 /* Copyright 2001 Sun Microsystems (thockin@sun.com) */
2 #include <stdio.h>
3 #include <stdlib.h>
4 #include "internal.h"
5 
6 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
7 
8 enum chip_type {
9 	RTL8139 = 1,
10 	RTL8139_K,
11 	RTL8139A,
12 	RTL8139A_G,
13 	RTL8139B,
14 	RTL8130,
15 	RTL8139C,
16 	RTL8100,
17 	RTL8100B_8139D,
18 	RTL8139Cp,
19 	RTL8101,
20 
21 	/* chips not handled by 8139too/8139cp module */
22 	RTL_GIGA_MAC_VER_01,
23 	RTL_GIGA_MAC_VER_02,
24 	RTL_GIGA_MAC_VER_03,
25 	RTL_GIGA_MAC_VER_04,
26 	RTL_GIGA_MAC_VER_05,
27 	RTL_GIGA_MAC_VER_06,
28 	RTL_GIGA_MAC_VER_07,
29 	RTL_GIGA_MAC_VER_08,
30 	RTL_GIGA_MAC_VER_09,
31 	RTL_GIGA_MAC_VER_10,
32 	RTL_GIGA_MAC_VER_11,
33 	RTL_GIGA_MAC_VER_12,
34 	RTL_GIGA_MAC_VER_13,
35 	RTL_GIGA_MAC_VER_14,
36 	RTL_GIGA_MAC_VER_15,
37 	RTL_GIGA_MAC_VER_16,
38 	RTL_GIGA_MAC_VER_17,
39 	RTL_GIGA_MAC_VER_18,
40 	RTL_GIGA_MAC_VER_19,
41 	RTL_GIGA_MAC_VER_20,
42 	RTL_GIGA_MAC_VER_21,
43 	RTL_GIGA_MAC_VER_22,
44 	RTL_GIGA_MAC_VER_23,
45 	RTL_GIGA_MAC_VER_24,
46 	RTL_GIGA_MAC_VER_25,
47 	RTL_GIGA_MAC_VER_26,
48 	RTL_GIGA_MAC_VER_27,
49 	RTL_GIGA_MAC_VER_28,
50 	RTL_GIGA_MAC_VER_29,
51 	RTL_GIGA_MAC_VER_30,
52 	RTL_GIGA_MAC_VER_31,
53 	RTL_GIGA_MAC_VER_32,
54 	RTL_GIGA_MAC_VER_33,
55 	RTL_GIGA_MAC_VER_34,
56 	RTL_GIGA_MAC_VER_35,
57 	RTL_GIGA_MAC_VER_36,
58 	RTL_GIGA_MAC_VER_37,
59 	RTL_GIGA_MAC_VER_38,
60 	RTL_GIGA_MAC_VER_39,
61 	RTL_GIGA_MAC_VER_40,
62 	RTL_GIGA_MAC_VER_41,
63 	RTL_GIGA_MAC_VER_42,
64 	RTL_GIGA_MAC_VER_43,
65 	RTL_GIGA_MAC_VER_44,
66 };
67 
68 static const char * const chip_names[] = {
69 	[RTL8139] =		"8139",
70 	[RTL8139_K] =		"8139-K",
71 	[RTL8139A] =		"8139A",
72 	[RTL8139A_G] =		"8139A-G",
73 	[RTL8139B] =		"8139B",
74 	[RTL8130] =		"8130",
75 	[RTL8139C] =		"8139C",
76 	[RTL8100] =		"8100",
77 	[RTL8100B_8139D] =	"8100B/8139D",
78 	[RTL8139Cp] =		"8139C+",
79 	[RTL8101] =		"8101",
80 
81 	/* chips not handled by 8139too/8139cp module */
82 	[RTL_GIGA_MAC_VER_01] = "8169",
83 	[RTL_GIGA_MAC_VER_02] = "8169s",
84 	[RTL_GIGA_MAC_VER_03] = "8110s",
85 	[RTL_GIGA_MAC_VER_04] = "8169sb/8110sb",
86 	[RTL_GIGA_MAC_VER_05] = "8169sc/8110sc",
87 	[RTL_GIGA_MAC_VER_06] = "8169sc/8110sc",
88 	[RTL_GIGA_MAC_VER_07] = "8102e",
89 	[RTL_GIGA_MAC_VER_08] = "8102e",
90 	[RTL_GIGA_MAC_VER_09] = "8102e",
91 	[RTL_GIGA_MAC_VER_10] = "8101e",
92 	[RTL_GIGA_MAC_VER_11] = "8168b/8111b",
93 	[RTL_GIGA_MAC_VER_12] = "8168b/8111b",
94 	[RTL_GIGA_MAC_VER_13] = "8101e",
95 	[RTL_GIGA_MAC_VER_14] = "8100e",
96 	[RTL_GIGA_MAC_VER_15] = "8100e",
97 	[RTL_GIGA_MAC_VER_16] = "8101e",
98 	[RTL_GIGA_MAC_VER_17] = "8168b/8111b",
99 	[RTL_GIGA_MAC_VER_18] = "8168cp/8111cp",
100 	[RTL_GIGA_MAC_VER_19] = "8168c/8111c",
101 	[RTL_GIGA_MAC_VER_20] = "8168c/8111c",
102 	[RTL_GIGA_MAC_VER_21] = "8168c/8111c",
103 	[RTL_GIGA_MAC_VER_22] = "8168c/8111c",
104 	[RTL_GIGA_MAC_VER_23] = "8168cp/8111cp",
105 	[RTL_GIGA_MAC_VER_24] = "8168cp/8111cp",
106 	[RTL_GIGA_MAC_VER_25] = "8168d/8111d",
107 	[RTL_GIGA_MAC_VER_26] = "8168d/8111d",
108 	[RTL_GIGA_MAC_VER_27] = "8168dp/8111dp",
109 	[RTL_GIGA_MAC_VER_28] = "8168dp/8111dp",
110 	[RTL_GIGA_MAC_VER_29] = "8105e",
111 	[RTL_GIGA_MAC_VER_30] = "8105e",
112 	[RTL_GIGA_MAC_VER_31] = "8168dp/8111dp",
113 	[RTL_GIGA_MAC_VER_32] = "8168e/8111e",
114 	[RTL_GIGA_MAC_VER_33] = "8168e/8111e",
115 	[RTL_GIGA_MAC_VER_34] = "8168evl/8111evl",
116 	[RTL_GIGA_MAC_VER_35] = "8168f/8111f",
117 	[RTL_GIGA_MAC_VER_36] = "8168f/8111f",
118 	[RTL_GIGA_MAC_VER_37] = "8402",
119 	[RTL_GIGA_MAC_VER_38] = "8411",
120 	[RTL_GIGA_MAC_VER_39] = "8106e",
121 	[RTL_GIGA_MAC_VER_40] = "8168g/8111g",
122 	[RTL_GIGA_MAC_VER_41] = "8168g/8111g",
123 	[RTL_GIGA_MAC_VER_42] = "8168g/8111g",
124 	[RTL_GIGA_MAC_VER_43] = "8106e",
125 	[RTL_GIGA_MAC_VER_44] = "8411",
126 };
127 
128 static struct chip_info {
129 	u32 id_mask;
130 	u32 id_val;
131 	int mac_version;
132 } rtl_info_tbl[] = {
133 	{ 0xfcc00000, 0x40000000,	RTL8139 },
134 	{ 0xfcc00000, 0x60000000,	RTL8139_K },
135 	{ 0xfcc00000, 0x70000000,	RTL8139A },
136 	{ 0xfcc00000, 0x70800000,	RTL8139A_G },
137 	{ 0xfcc00000, 0x78000000,	RTL8139B },
138 	{ 0xfcc00000, 0x7c000000,	RTL8130 },
139 	{ 0xfcc00000, 0x74000000,	RTL8139C },
140 	{ 0xfcc00000, 0x78800000,	RTL8100 },
141 	{ 0xfcc00000, 0x74400000,	RTL8100B_8139D },
142 	{ 0xfcc00000, 0x74800000,	RTL8139Cp },
143 	{ 0xfcc00000, 0x74c00000,	RTL8101 },
144 
145 	/* chips not handled by 8139too/8139cp module */
146 	/* 8168G family. */
147 	{ 0x7cf00000, 0x5c800000,	RTL_GIGA_MAC_VER_44 },
148 	{ 0x7cf00000, 0x50900000,	RTL_GIGA_MAC_VER_42 },
149 	{ 0x7cf00000, 0x4c100000,	RTL_GIGA_MAC_VER_41 },
150 	{ 0x7cf00000, 0x4c000000,	RTL_GIGA_MAC_VER_40 },
151 
152 	/* 8168F family. */
153 	{ 0x7c800000, 0x48800000,	RTL_GIGA_MAC_VER_38 },
154 	{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
155 	{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },
156 
157 	/* 8168E family. */
158 	{ 0x7c800000, 0x2c800000,	RTL_GIGA_MAC_VER_34 },
159 	{ 0x7cf00000, 0x2c200000,	RTL_GIGA_MAC_VER_33 },
160 	{ 0x7cf00000, 0x2c100000,	RTL_GIGA_MAC_VER_32 },
161 	{ 0x7c800000, 0x2c000000,	RTL_GIGA_MAC_VER_33 },
162 
163 	/* 8168D family. */
164 	{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
165 	{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
166 	{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
167 
168 	/* 8168DP family. */
169 	{ 0x7cf00000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
170 	{ 0x7cf00000, 0x28a00000,	RTL_GIGA_MAC_VER_28 },
171 	{ 0x7cf00000, 0x28b00000,	RTL_GIGA_MAC_VER_31 },
172 
173 	/* 8168C family. */
174 	{ 0x7cf00000, 0x3cb00000,	RTL_GIGA_MAC_VER_24 },
175 	{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
176 	{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
177 	{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
178 	{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
179 	{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
180 	{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
181 	{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
182 	{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
183 
184 	/* 8168B family. */
185 	{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
186 	{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
187 	{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
188 	{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },
189 
190 	/* 8101 family. */
191 	{ 0x7cf00000, 0x44900000,	RTL_GIGA_MAC_VER_39 },
192 	{ 0x7c800000, 0x44800000,	RTL_GIGA_MAC_VER_39 },
193 	{ 0x7c800000, 0x44000000,	RTL_GIGA_MAC_VER_37 },
194 	{ 0x7cf00000, 0x40b00000,	RTL_GIGA_MAC_VER_30 },
195 	{ 0x7cf00000, 0x40a00000,	RTL_GIGA_MAC_VER_30 },
196 	{ 0x7cf00000, 0x40900000,	RTL_GIGA_MAC_VER_29 },
197 	{ 0x7c800000, 0x40800000,	RTL_GIGA_MAC_VER_30 },
198 	{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
199 	{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
200 	{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
201 	{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
202 	{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
203 	{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
204 	{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
205 	{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
206 	{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
207 	{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
208 	{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
209 	{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
210 	/* FIXME: where did these entries come from ? -- FR */
211 	{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
212 	{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },
213 
214 	/* 8110 family. */
215 	{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
216 	{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
217 	{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
218 	{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
219 	{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
220 	{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },
221 
222 	{ }
223 };
224 
225 static void
print_intr_bits(u16 mask)226 print_intr_bits(u16 mask)
227 {
228 	fprintf(stdout,
229 		"      %s%s%s%s%s%s%s%s%s%s%s\n",
230 		mask & (1 << 15)	? "SERR " : "",
231 		mask & (1 << 14)	? "TimeOut " : "",
232 		mask & (1 << 8)		? "SWInt " : "",
233 		mask & (1 << 7)		? "TxNoBuf " : "",
234 		mask & (1 << 6)		? "RxFIFO " : "",
235 		mask & (1 << 5)		? "LinkChg " : "",
236 		mask & (1 << 4)		? "RxNoBuf " : "",
237 		mask & (1 << 3)		? "TxErr " : "",
238 		mask & (1 << 2)		? "TxOK " : "",
239 		mask & (1 << 1)		? "RxErr " : "",
240 		mask & (1 << 0)		? "RxOK " : "");
241 }
242 
243 int
realtek_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)244 realtek_dump_regs(struct ethtool_drvinfo *info maybe_unused,
245 		  struct ethtool_regs *regs)
246 {
247 	u32 *data = (u32 *) regs->data;
248 	u8 *data8 = (u8 *) regs->data;
249 	u32 v;
250 	struct chip_info *ci;
251 	unsigned int board_type;
252 
253 	v = data[0x40 >> 2]; /* TxConfig */
254 
255 	ci = &rtl_info_tbl[0];
256 	while (ci->mac_version) {
257 		if ((v & ci->id_mask) == ci->id_val)
258 			break;
259 		ci++;
260 	}
261 	board_type = ci->mac_version;
262 	if (!board_type) {
263 		fprintf(stderr, "Unknown RealTek chip (TxConfig: 0x%08x)\n", v);
264 		return 91;
265 	}
266 
267 	fprintf(stdout,
268 		"RealTek RTL%s registers:\n"
269 		"--------------------------------------------------------\n",
270 		chip_names[board_type]);
271 
272 	fprintf(stdout,
273 		"0x00: MAC Address                      %02x:%02x:%02x:%02x:%02x:%02x\n",
274 		data8[0x00],
275 		data8[0x01],
276 		data8[0x02],
277 		data8[0x03],
278 		data8[0x04],
279 		data8[0x05]);
280 
281 	fprintf(stdout,
282 		"0x08: Multicast Address Filter     0x%08x 0x%08x\n",
283 		data[0x08 >> 2],
284 		data[0x0c >> 2]);
285 
286 	if (board_type == RTL8139Cp || board_type >= RTL_GIGA_MAC_VER_01) {
287 	fprintf(stdout,
288 		"0x10: Dump Tally Counter Command   0x%08x 0x%08x\n",
289 		data[0x10 >> 2],
290 		data[0x14 >> 2]);
291 
292 	fprintf(stdout,
293 		"0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x\n",
294 		data[0x20 >> 2],
295 		data[0x24 >> 2]);
296 
297 	fprintf(stdout,
298 		"0x28: Tx High Priority Ring Addr   0x%08x 0x%08x\n",
299 		data[0x28 >> 2],
300 		data[0x2C >> 2]);
301 	} else {
302 	fprintf(stdout,
303 		"0x10: Transmit Status Desc 0                  0x%08x\n"
304 		"0x14: Transmit Status Desc 1                  0x%08x\n"
305 		"0x18: Transmit Status Desc 2                  0x%08x\n"
306 		"0x1C: Transmit Status Desc 3                  0x%08x\n",
307 		data[0x10 >> 2],
308 		data[0x14 >> 2],
309 		data[0x18 >> 2],
310 		data[0x1C >> 2]);
311 	fprintf(stdout,
312 		"0x20: Transmit Start Addr  0                  0x%08x\n"
313 		"0x24: Transmit Start Addr  1                  0x%08x\n"
314 		"0x28: Transmit Start Addr  2                  0x%08x\n"
315 		"0x2C: Transmit Start Addr  3                  0x%08x\n",
316 		data[0x20 >> 2],
317 		data[0x24 >> 2],
318 		data[0x28 >> 2],
319 		data[0x2C >> 2]);
320 	}
321 
322 	if (board_type < RTL_GIGA_MAC_VER_11 ||
323 		board_type > RTL_GIGA_MAC_VER_17) {
324 	if (board_type >= RTL_GIGA_MAC_VER_01) {
325 	fprintf(stdout,
326 		"0x30: Flash memory read/write                 0x%08x\n",
327 		data[0x30 >> 2]);
328 	} else {
329 	fprintf(stdout,
330 		"0x30: Rx buffer addr (C mode)                 0x%08x\n",
331 		data[0x30 >> 2]);
332 	}
333 	}
334 
335 	v = data8[0x36];
336 	fprintf(stdout,
337 		"0x34: Early Rx Byte Count                       %8u\n"
338 		"0x36: Early Rx Status                               0x%02x\n",
339 		data[0x34 >> 2] & 0xffff,
340 		v);
341 
342 	if (v & 0xf) {
343 	fprintf(stdout,
344 		"      %s%s%s%s\n",
345 		v & (1 << 3) ? "ERxGood " : "",
346 		v & (1 << 2) ? "ERxBad " : "",
347 		v & (1 << 1) ? "ERxOverWrite " : "",
348 		v & (1 << 0) ? "ERxOK " : "");
349 	}
350 
351 	v = data8[0x37];
352 	fprintf(stdout,
353 		"0x37: Command                                       0x%02x\n"
354 		"      Rx %s, Tx %s%s\n",
355 		data8[0x37],
356 		v & (1 << 3) ? "on" : "off",
357 		v & (1 << 2) ? "on" : "off",
358 		v & (1 << 4) ? ", RESET" : "");
359 
360 	if (board_type < RTL_GIGA_MAC_VER_01) {
361 	fprintf(stdout,
362 		"0x38: Current Address of Packet Read (C mode)     0x%04x\n"
363 		"0x3A: Current Rx buffer address (C mode)          0x%04x\n",
364 		data[0x38 >> 2] & 0xffff,
365 		data[0x38 >> 2] >> 16);
366 	}
367 
368 	fprintf(stdout,
369 		"0x3C: Interrupt Mask                              0x%04x\n",
370 		data[0x3c >> 2] & 0xffff);
371 	print_intr_bits(data[0x3c >> 2] & 0xffff);
372 	fprintf(stdout,
373 		"0x3E: Interrupt Status                            0x%04x\n",
374 		data[0x3c >> 2] >> 16);
375 	print_intr_bits(data[0x3c >> 2] >> 16);
376 
377 	fprintf(stdout,
378 		"0x40: Tx Configuration                        0x%08x\n"
379 		"0x44: Rx Configuration                        0x%08x\n"
380 		"0x48: Timer count                             0x%08x\n"
381 		"0x4C: Missed packet counter                     0x%06x\n",
382 		data[0x40 >> 2],
383 		data[0x44 >> 2],
384 		data[0x48 >> 2],
385 		data[0x4C >> 2] & 0xffffff);
386 
387 	fprintf(stdout,
388 		"0x50: EEPROM Command                                0x%02x\n"
389 		"0x51: Config 0                                      0x%02x\n"
390 		"0x52: Config 1                                      0x%02x\n",
391 		data8[0x50],
392 		data8[0x51],
393 		data8[0x52]);
394 
395 	if (board_type >= RTL_GIGA_MAC_VER_01) {
396 	fprintf(stdout,
397 		"0x53: Config 2                                      0x%02x\n"
398 		"0x54: Config 3                                      0x%02x\n"
399 		"0x55: Config 4                                      0x%02x\n"
400 		"0x56: Config 5                                      0x%02x\n",
401 		data8[0x53],
402 		data8[0x54],
403 		data8[0x55],
404 		data8[0x56]);
405 	fprintf(stdout,
406 		"0x58: Timer interrupt                         0x%08x\n",
407 		data[0x58 >> 2]);
408 	}
409 	else {
410 	if (board_type >= RTL8139A) {
411 	fprintf(stdout,
412 		"0x54: Timer interrupt                         0x%08x\n",
413 		data[0x54 >> 2]);
414 	}
415 	fprintf(stdout,
416 		"0x58: Media status                                  0x%02x\n",
417 		data8[0x58]);
418 	if (board_type >= RTL8139A) {
419 	fprintf(stdout,
420 		"0x59: Config 3                                      0x%02x\n",
421 		data8[0x59]);
422 	}
423 	if (board_type >= RTL8139B) {
424 	fprintf(stdout,
425 		"0x5A: Config 4                                      0x%02x\n",
426 		data8[0x5A]);
427 	}
428 	}
429 
430 	fprintf(stdout,
431 		"0x5C: Multiple Interrupt Select                   0x%04x\n",
432 		data[0x5c >> 2] & 0xffff);
433 
434 	if (board_type >= RTL_GIGA_MAC_VER_01) {
435 	fprintf(stdout,
436 		"0x60: PHY access                              0x%08x\n",
437 		data[0x60 >> 2]);
438 
439 	if (board_type < RTL_GIGA_MAC_VER_11 ||
440 		board_type > RTL_GIGA_MAC_VER_17) {
441 	fprintf(stdout,
442 		"0x64: TBI control and status                  0x%08x\n",
443 		data[0x64 >> 2]);
444 	fprintf(stdout,
445 		"0x68: TBI Autonegotiation advertisement (ANAR)    0x%04x\n"
446 		"0x6A: TBI Link partner ability (LPAR)             0x%04x\n",
447 		data[0x68 >> 2] & 0xffff,
448 		data[0x68 >> 2] >> 16);
449 	}
450 
451 	fprintf(stdout,
452 		"0x6C: PHY status                                    0x%02x\n",
453 		data8[0x6C]);
454 
455 	fprintf(stdout,
456 		"0x84: PM wakeup frame 0            0x%08x 0x%08x\n"
457 		"0x8C: PM wakeup frame 1            0x%08x 0x%08x\n",
458 		data[0x84 >> 2],
459 		data[0x88 >> 2],
460 		data[0x8C >> 2],
461 		data[0x90 >> 2]);
462 
463 	fprintf(stdout,
464 		"0x94: PM wakeup frame 2 (low)      0x%08x 0x%08x\n"
465 		"0x9C: PM wakeup frame 2 (high)     0x%08x 0x%08x\n",
466 		data[0x94 >> 2],
467 		data[0x98 >> 2],
468 		data[0x9C >> 2],
469 		data[0xA0 >> 2]);
470 
471 	fprintf(stdout,
472 		"0xA4: PM wakeup frame 3 (low)      0x%08x 0x%08x\n"
473 		"0xAC: PM wakeup frame 3 (high)     0x%08x 0x%08x\n",
474 		data[0xA4 >> 2],
475 		data[0xA8 >> 2],
476 		data[0xAC >> 2],
477 		data[0xB0 >> 2]);
478 
479 	fprintf(stdout,
480 		"0xB4: PM wakeup frame 4 (low)      0x%08x 0x%08x\n"
481 		"0xBC: PM wakeup frame 4 (high)     0x%08x 0x%08x\n",
482 		data[0xB4 >> 2],
483 		data[0xB8 >> 2],
484 		data[0xBC >> 2],
485 		data[0xC0 >> 2]);
486 
487 	fprintf(stdout,
488 		"0xC4: Wakeup frame 0 CRC                          0x%04x\n"
489 		"0xC6: Wakeup frame 1 CRC                          0x%04x\n"
490 		"0xC8: Wakeup frame 2 CRC                          0x%04x\n"
491 		"0xCA: Wakeup frame 3 CRC                          0x%04x\n"
492 		"0xCC: Wakeup frame 4 CRC                          0x%04x\n",
493 		data[0xC4 >> 2] & 0xffff,
494 		data[0xC4 >> 2] >> 16,
495 		data[0xC8 >> 2] & 0xffff,
496 		data[0xC8 >> 2] >> 16,
497 		data[0xCC >> 2] & 0xffff);
498 	fprintf(stdout,
499 		"0xDA: RX packet maximum size                      0x%04x\n",
500 		data[0xD8 >> 2] >> 16);
501 	}
502 	else {
503 	fprintf(stdout,
504 		"0x5E: PCI revision id                               0x%02x\n",
505 		data8[0x5e]);
506 	fprintf(stdout,
507 		"0x60: Transmit Status of All Desc (C mode)        0x%04x\n"
508 		"0x62: MII Basic Mode Control Register             0x%04x\n",
509 		data[0x60 >> 2] & 0xffff,
510 		data[0x60 >> 2] >> 16);
511 	fprintf(stdout,
512 		"0x64: MII Basic Mode Status Register              0x%04x\n"
513 		"0x66: MII Autonegotiation Advertising             0x%04x\n",
514 		data[0x64 >> 2] & 0xffff,
515 		data[0x64 >> 2] >> 16);
516 	fprintf(stdout,
517 		"0x68: MII Link Partner Ability                    0x%04x\n"
518 		"0x6A: MII Expansion                               0x%04x\n",
519 		data[0x68 >> 2] & 0xffff,
520 		data[0x68 >> 2] >> 16);
521 	fprintf(stdout,
522 		"0x6C: MII Disconnect counter                      0x%04x\n"
523 		"0x6E: MII False carrier sense counter             0x%04x\n",
524 		data[0x6C >> 2] & 0xffff,
525 		data[0x6C >> 2] >> 16);
526 	fprintf(stdout,
527 		"0x70: MII Nway test                               0x%04x\n"
528 		"0x72: MII RX_ER counter                           0x%04x\n",
529 		data[0x70 >> 2] & 0xffff,
530 		data[0x70 >> 2] >> 16);
531 	fprintf(stdout,
532 		"0x74: MII CS configuration                        0x%04x\n",
533 		data[0x74 >> 2] & 0xffff);
534 	if (board_type >= RTL8139_K) {
535 	fprintf(stdout,
536 		"0x78: PHY parameter 1                         0x%08x\n"
537 		"0x7C: Twister parameter                       0x%08x\n",
538 		data[0x78 >> 2],
539 		data[0x7C >> 2]);
540 	if (board_type >= RTL8139A) {
541 	fprintf(stdout,
542 		"0x80: PHY parameter 2                               0x%02x\n",
543 		data8[0x80]);
544 	}
545 	}
546 	if (board_type == RTL8139Cp) {
547 	fprintf(stdout,
548 		"0x82: Low addr of a Tx Desc w/ Tx DMA OK          0x%04x\n",
549 		data[0x80 >> 2] >> 16);
550 	} else if (board_type == RTL8130) {
551 	fprintf(stdout,
552 		"0x82: MII register                                  0x%02x\n",
553 		data8[0x82]);
554 	}
555 	if (board_type >= RTL8139A) {
556 	fprintf(stdout,
557 		"0x84: PM CRC for wakeup frame 0                     0x%02x\n"
558 		"0x85: PM CRC for wakeup frame 1                     0x%02x\n"
559 		"0x86: PM CRC for wakeup frame 2                     0x%02x\n"
560 		"0x87: PM CRC for wakeup frame 3                     0x%02x\n"
561 		"0x88: PM CRC for wakeup frame 4                     0x%02x\n"
562 		"0x89: PM CRC for wakeup frame 5                     0x%02x\n"
563 		"0x8A: PM CRC for wakeup frame 6                     0x%02x\n"
564 		"0x8B: PM CRC for wakeup frame 7                     0x%02x\n",
565 		data8[0x84],
566 		data8[0x85],
567 		data8[0x86],
568 		data8[0x87],
569 		data8[0x88],
570 		data8[0x89],
571 		data8[0x8A],
572 		data8[0x8B]);
573 	fprintf(stdout,
574 		"0x8C: PM wakeup frame 0            0x%08x 0x%08x\n"
575 		"0x94: PM wakeup frame 1            0x%08x 0x%08x\n"
576 		"0x9C: PM wakeup frame 2            0x%08x 0x%08x\n"
577 		"0xA4: PM wakeup frame 3            0x%08x 0x%08x\n"
578 		"0xAC: PM wakeup frame 4            0x%08x 0x%08x\n"
579 		"0xB4: PM wakeup frame 5            0x%08x 0x%08x\n"
580 		"0xBC: PM wakeup frame 6            0x%08x 0x%08x\n"
581 		"0xC4: PM wakeup frame 7            0x%08x 0x%08x\n",
582 		data[0x8C >> 2],
583 		data[0x90 >> 2],
584 		data[0x94 >> 2],
585 		data[0x98 >> 2],
586 		data[0x9C >> 2],
587 		data[0xA0 >> 2],
588 		data[0xA4 >> 2],
589 		data[0xA8 >> 2],
590 		data[0xAC >> 2],
591 		data[0xB0 >> 2],
592 		data[0xB4 >> 2],
593 		data[0xB8 >> 2],
594 		data[0xBC >> 2],
595 		data[0xC0 >> 2],
596 		data[0xC4 >> 2],
597 		data[0xC8 >> 2]);
598 	fprintf(stdout,
599 		"0xCC: PM LSB CRC for wakeup frame 0                 0x%02x\n"
600 		"0xCD: PM LSB CRC for wakeup frame 1                 0x%02x\n"
601 		"0xCE: PM LSB CRC for wakeup frame 2                 0x%02x\n"
602 		"0xCF: PM LSB CRC for wakeup frame 3                 0x%02x\n"
603 		"0xD0: PM LSB CRC for wakeup frame 4                 0x%02x\n"
604 		"0xD1: PM LSB CRC for wakeup frame 5                 0x%02x\n"
605 		"0xD2: PM LSB CRC for wakeup frame 6                 0x%02x\n"
606 		"0xD3: PM LSB CRC for wakeup frame 7                 0x%02x\n",
607 		data8[0xCC],
608 		data8[0xCD],
609 		data8[0xCE],
610 		data8[0xCF],
611 		data8[0xD0],
612 		data8[0xD1],
613 		data8[0xD2],
614 		data8[0xD3]);
615 	}
616 	if (board_type >= RTL8139B) {
617 	if (board_type != RTL8100 && board_type != RTL8100B_8139D &&
618 	    board_type != RTL8101)
619 	fprintf(stdout,
620 		"0xD4: Flash memory read/write                 0x%08x\n",
621 		data[0xD4 >> 2]);
622 	if (board_type != RTL8130)
623 	fprintf(stdout,
624 		"0xD8: Config 5                                      0x%02x\n",
625 		data8[0xD8]);
626 	}
627 	}
628 
629 	if (board_type == RTL8139Cp || board_type >= RTL_GIGA_MAC_VER_01) {
630 	v = data[0xE0 >> 2] & 0xffff;
631 	fprintf(stdout,
632 		"0xE0: C+ Command                                  0x%04x\n",
633 		v);
634 	if (v & (1 << 9))
635 		fprintf(stdout, "      Big-endian mode\n");
636 	if (v & (1 << 8))
637 		fprintf(stdout, "      Home LAN enable\n");
638 	if (v & (1 << 6))
639 		fprintf(stdout, "      VLAN de-tagging\n");
640 	if (v & (1 << 5))
641 		fprintf(stdout, "      RX checksumming\n");
642 	if (v & (1 << 4))
643 		fprintf(stdout, "      PCI 64-bit DAC\n");
644 	if (v & (1 << 3))
645 		fprintf(stdout, "      PCI Multiple RW\n");
646 
647 	v = data[0xe0 >> 2] >> 16;
648 	fprintf(stdout,
649 		"0xE2: Interrupt Mitigation                        0x%04x\n"
650 		"      TxTimer:       %u\n"
651 		"      TxPackets:     %u\n"
652 		"      RxTimer:       %u\n"
653 		"      RxPackets:     %u\n",
654 		v,
655 		v >> 12,
656 		(v >> 8) & 0xf,
657 		(v >> 4) & 0xf,
658 		v & 0xf);
659 
660 	fprintf(stdout,
661 		"0xE4: Rx Ring Addr                 0x%08x 0x%08x\n",
662 		data[0xE4 >> 2],
663 		data[0xE8 >> 2]);
664 
665 	fprintf(stdout,
666 		"0xEC: Early Tx threshold                            0x%02x\n",
667 		data8[0xEC]);
668 
669 	if (board_type == RTL8139Cp) {
670 	fprintf(stdout,
671 		"0xFC: External MII register                   0x%08x\n",
672 		data[0xFC >> 2]);
673 	} else if (board_type >= RTL_GIGA_MAC_VER_01 &&
674 		(board_type < RTL_GIGA_MAC_VER_11 ||
675 		board_type > RTL_GIGA_MAC_VER_17)) {
676 	fprintf(stdout,
677 		"0xF0: Func Event                              0x%08x\n"
678 		"0xF4: Func Event Mask                         0x%08x\n"
679 		"0xF8: Func Preset State                       0x%08x\n"
680 		"0xFC: Func Force Event                        0x%08x\n",
681 		data[0xF0 >> 2],
682 		data[0xF4 >> 2],
683 		data[0xF8 >> 2],
684 		data[0xFC >> 2]);
685 	}
686 	}
687 
688 	return 0;
689 }
690