1 /*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7
8 /*******************************************************************************
9 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a
10 * plug-in component to the Secure Monitor, registered as a runtime service. The
11 * SPD is expected to be a functional extension of the Secure Payload (SP) that
12 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting
13 * the Trusted OS/Applications range to the dispatcher. The SPD will either
14 * handle the request locally or delegate it to the Secure Payload. It is also
15 * responsible for initialising and maintaining communication with the SP.
16 ******************************************************************************/
17 #include <assert.h>
18 #include <errno.h>
19 #include <stddef.h>
20 #include <string.h>
21
22 #include <arch_helpers.h>
23 #include <bl31/bl31.h>
24 #include <bl31/ehf.h>
25 #include <bl32/tsp/tsp.h>
26 #include <common/bl_common.h>
27 #include <common/debug.h>
28 #include <common/runtime_svc.h>
29 #include <lib/el3_runtime/context_mgmt.h>
30 #include <plat/common/platform.h>
31 #include <tools_share/uuid.h>
32
33 #include "tspd_private.h"
34
35 /*******************************************************************************
36 * Address of the entrypoint vector table in the Secure Payload. It is
37 * initialised once on the primary core after a cold boot.
38 ******************************************************************************/
39 tsp_vectors_t *tsp_vectors;
40
41 /*******************************************************************************
42 * Array to keep track of per-cpu Secure Payload state
43 ******************************************************************************/
44 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
45
46
47 /* TSP UID */
48 DEFINE_SVC_UUID2(tsp_uuid,
49 0xa056305b, 0x9132, 0x7b42, 0x98, 0x11,
50 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa);
51
52 int32_t tspd_init(void);
53
54 /*
55 * This helper function handles Secure EL1 preemption. The preemption could be
56 * due Non Secure interrupts or EL3 interrupts. In both the cases we context
57 * switch to the normal world and in case of EL3 interrupts, it will again be
58 * routed to EL3 which will get handled at the exception vectors.
59 */
tspd_handle_sp_preemption(void * handle)60 uint64_t tspd_handle_sp_preemption(void *handle)
61 {
62 cpu_context_t *ns_cpu_context;
63
64 assert(handle == cm_get_context(SECURE));
65 cm_el1_sysregs_context_save(SECURE);
66 /* Get a reference to the non-secure context */
67 ns_cpu_context = cm_get_context(NON_SECURE);
68 assert(ns_cpu_context);
69
70 /*
71 * To allow Secure EL1 interrupt handler to re-enter TSP while TSP
72 * is preempted, the secure system register context which will get
73 * overwritten must be additionally saved. This is currently done
74 * by the TSPD S-EL1 interrupt handler.
75 */
76
77 /*
78 * Restore non-secure state.
79 */
80 cm_el1_sysregs_context_restore(NON_SECURE);
81 cm_set_next_eret_context(NON_SECURE);
82
83 /*
84 * The TSP was preempted during execution of a Yielding SMC Call.
85 * Return back to the normal world with SMC_PREEMPTED as error
86 * code in x0.
87 */
88 SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
89 }
90
91 /*******************************************************************************
92 * This function is the handler registered for S-EL1 interrupts by the TSPD. It
93 * validates the interrupt and upon success arranges entry into the TSP at
94 * 'tsp_sel1_intr_entry()' for handling the interrupt.
95 ******************************************************************************/
tspd_sel1_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)96 static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
97 uint32_t flags,
98 void *handle,
99 void *cookie)
100 {
101 uint32_t linear_id;
102 tsp_context_t *tsp_ctx;
103
104 /* Check the security state when the exception was generated */
105 assert(get_interrupt_src_ss(flags) == NON_SECURE);
106
107 /* Sanity check the pointer to this cpu's context */
108 assert(handle == cm_get_context(NON_SECURE));
109
110 /* Save the non-secure context before entering the TSP */
111 cm_el1_sysregs_context_save(NON_SECURE);
112
113 /* Get a reference to this cpu's TSP context */
114 linear_id = plat_my_core_pos();
115 tsp_ctx = &tspd_sp_context[linear_id];
116 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
117
118 /*
119 * Determine if the TSP was previously preempted. Its last known
120 * context has to be preserved in this case.
121 * The TSP should return control to the TSPD after handling this
122 * S-EL1 interrupt. Preserve essential EL3 context to allow entry into
123 * the TSP at the S-EL1 interrupt entry point using the 'cpu_context'
124 * structure. There is no need to save the secure system register
125 * context since the TSP is supposed to preserve it during S-EL1
126 * interrupt handling.
127 */
128 if (get_yield_smc_active_flag(tsp_ctx->state)) {
129 tsp_ctx->saved_spsr_el3 = (uint32_t)SMC_GET_EL3(&tsp_ctx->cpu_ctx,
130 CTX_SPSR_EL3);
131 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
132 CTX_ELR_EL3);
133 #if TSP_NS_INTR_ASYNC_PREEMPT
134 /*Need to save the previously interrupted secure context */
135 memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE);
136 #endif
137 }
138
139 cm_el1_sysregs_context_restore(SECURE);
140 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry,
141 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS));
142
143 cm_set_next_eret_context(SECURE);
144
145 /*
146 * Tell the TSP that it has to handle a S-EL1 interrupt synchronously.
147 * Also the instruction in normal world where the interrupt was
148 * generated is passed for debugging purposes. It is safe to retrieve
149 * this address from ELR_EL3 as the secure context will not take effect
150 * until el3_exit().
151 */
152 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_SEL1_INTR_AND_RETURN, read_elr_el3());
153 }
154
155 #if TSP_NS_INTR_ASYNC_PREEMPT
156 /*******************************************************************************
157 * This function is the handler registered for Non secure interrupts by the
158 * TSPD. It validates the interrupt and upon success arranges entry into the
159 * normal world for handling the interrupt.
160 ******************************************************************************/
tspd_ns_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)161 static uint64_t tspd_ns_interrupt_handler(uint32_t id,
162 uint32_t flags,
163 void *handle,
164 void *cookie)
165 {
166 /* Check the security state when the exception was generated */
167 assert(get_interrupt_src_ss(flags) == SECURE);
168
169 /*
170 * Disable the routing of NS interrupts from secure world to EL3 while
171 * interrupted on this core.
172 */
173 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
174
175 return tspd_handle_sp_preemption(handle);
176 }
177 #endif
178
179 /*******************************************************************************
180 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type
181 * (aarch32/aarch64) if not already known and initialises the context for entry
182 * into the SP for its initialisation.
183 ******************************************************************************/
tspd_setup(void)184 static int32_t tspd_setup(void)
185 {
186 entry_point_info_t *tsp_ep_info;
187 uint32_t linear_id;
188
189 linear_id = plat_my_core_pos();
190
191 /*
192 * Get information about the Secure Payload (BL32) image. Its
193 * absence is a critical failure. TODO: Add support to
194 * conditionally include the SPD service
195 */
196 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
197 if (!tsp_ep_info) {
198 WARN("No TSP provided by BL2 boot loader, Booting device"
199 " without TSP initialization. SMC`s destined for TSP"
200 " will return SMC_UNK\n");
201 return 1;
202 }
203
204 /*
205 * If there's no valid entry point for SP, we return a non-zero value
206 * signalling failure initializing the service. We bail out without
207 * registering any handlers
208 */
209 if (!tsp_ep_info->pc)
210 return 1;
211
212 /*
213 * We could inspect the SP image and determine its execution
214 * state i.e whether AArch32 or AArch64. Assuming it's AArch64
215 * for the time being.
216 */
217 tspd_init_tsp_ep_state(tsp_ep_info,
218 TSP_AARCH64,
219 tsp_ep_info->pc,
220 &tspd_sp_context[linear_id]);
221
222 #if TSP_INIT_ASYNC
223 bl31_set_next_image_type(SECURE);
224 #else
225 /*
226 * All TSPD initialization done. Now register our init function with
227 * BL31 for deferred invocation
228 */
229 bl31_register_bl32_init(&tspd_init);
230 #endif
231 return 0;
232 }
233
234 /*******************************************************************************
235 * This function passes control to the Secure Payload image (BL32) for the first
236 * time on the primary cpu after a cold boot. It assumes that a valid secure
237 * context has already been created by tspd_setup() which can be directly used.
238 * It also assumes that a valid non-secure context has been initialised by PSCI
239 * so it does not need to save and restore any non-secure state. This function
240 * performs a synchronous entry into the Secure payload. The SP passes control
241 * back to this routine through a SMC.
242 ******************************************************************************/
tspd_init(void)243 int32_t tspd_init(void)
244 {
245 uint32_t linear_id = plat_my_core_pos();
246 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
247 entry_point_info_t *tsp_entry_point;
248 uint64_t rc;
249
250 /*
251 * Get information about the Secure Payload (BL32) image. Its
252 * absence is a critical failure.
253 */
254 tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
255 assert(tsp_entry_point);
256
257 cm_init_my_context(tsp_entry_point);
258
259 /*
260 * Arrange for an entry into the test secure payload. It will be
261 * returned via TSP_ENTRY_DONE case
262 */
263 rc = tspd_synchronous_sp_entry(tsp_ctx);
264 assert(rc != 0);
265
266 return rc;
267 }
268
269
270 /*******************************************************************************
271 * This function is responsible for handling all SMCs in the Trusted OS/App
272 * range from the non-secure state as defined in the SMC Calling Convention
273 * Document. It is also responsible for communicating with the Secure payload
274 * to delegate work and return results back to the non-secure state. Lastly it
275 * will also return any information that the secure payload needs to do the
276 * work assigned to it.
277 ******************************************************************************/
tspd_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)278 static uintptr_t tspd_smc_handler(uint32_t smc_fid,
279 u_register_t x1,
280 u_register_t x2,
281 u_register_t x3,
282 u_register_t x4,
283 void *cookie,
284 void *handle,
285 u_register_t flags)
286 {
287 cpu_context_t *ns_cpu_context;
288 uint32_t linear_id = plat_my_core_pos(), ns;
289 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
290 uint64_t rc;
291 #if TSP_INIT_ASYNC
292 entry_point_info_t *next_image_info;
293 #endif
294
295 /* Determine which security state this SMC originated from */
296 ns = is_caller_non_secure(flags);
297
298 switch (smc_fid) {
299
300 /*
301 * This function ID is used by TSP to indicate that it was
302 * preempted by a normal world IRQ.
303 *
304 */
305 case TSP_PREEMPTED:
306 if (ns)
307 SMC_RET1(handle, SMC_UNK);
308
309 return tspd_handle_sp_preemption(handle);
310
311 /*
312 * This function ID is used only by the TSP to indicate that it has
313 * finished handling a S-EL1 interrupt or was preempted by a higher
314 * priority pending EL3 interrupt. Execution should resume
315 * in the normal world.
316 */
317 case TSP_HANDLED_S_EL1_INTR:
318 if (ns)
319 SMC_RET1(handle, SMC_UNK);
320
321 assert(handle == cm_get_context(SECURE));
322
323 /*
324 * Restore the relevant EL3 state which saved to service
325 * this SMC.
326 */
327 if (get_yield_smc_active_flag(tsp_ctx->state)) {
328 SMC_SET_EL3(&tsp_ctx->cpu_ctx,
329 CTX_SPSR_EL3,
330 tsp_ctx->saved_spsr_el3);
331 SMC_SET_EL3(&tsp_ctx->cpu_ctx,
332 CTX_ELR_EL3,
333 tsp_ctx->saved_elr_el3);
334 #if TSP_NS_INTR_ASYNC_PREEMPT
335 /*
336 * Need to restore the previously interrupted
337 * secure context.
338 */
339 memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx,
340 TSPD_SP_CTX_SIZE);
341 #endif
342 }
343
344 /* Get a reference to the non-secure context */
345 ns_cpu_context = cm_get_context(NON_SECURE);
346 assert(ns_cpu_context);
347
348 /*
349 * Restore non-secure state. There is no need to save the
350 * secure system register context since the TSP was supposed
351 * to preserve it during S-EL1 interrupt handling.
352 */
353 cm_el1_sysregs_context_restore(NON_SECURE);
354 cm_set_next_eret_context(NON_SECURE);
355
356 SMC_RET0((uint64_t) ns_cpu_context);
357
358 /*
359 * This function ID is used only by the SP to indicate it has
360 * finished initialising itself after a cold boot
361 */
362 case TSP_ENTRY_DONE:
363 if (ns)
364 SMC_RET1(handle, SMC_UNK);
365
366 /*
367 * Stash the SP entry points information. This is done
368 * only once on the primary cpu
369 */
370 assert(tsp_vectors == NULL);
371 tsp_vectors = (tsp_vectors_t *) x1;
372
373 if (tsp_vectors) {
374 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
375
376 /*
377 * TSP has been successfully initialized. Register power
378 * management hooks with PSCI
379 */
380 psci_register_spd_pm_hook(&tspd_pm);
381
382 /*
383 * Register an interrupt handler for S-EL1 interrupts
384 * when generated during code executing in the
385 * non-secure state.
386 */
387 flags = 0;
388 set_interrupt_rm_flag(flags, NON_SECURE);
389 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
390 tspd_sel1_interrupt_handler,
391 flags);
392 if (rc)
393 panic();
394
395 #if TSP_NS_INTR_ASYNC_PREEMPT
396 /*
397 * Register an interrupt handler for NS interrupts when
398 * generated during code executing in secure state are
399 * routed to EL3.
400 */
401 flags = 0;
402 set_interrupt_rm_flag(flags, SECURE);
403
404 rc = register_interrupt_type_handler(INTR_TYPE_NS,
405 tspd_ns_interrupt_handler,
406 flags);
407 if (rc)
408 panic();
409
410 /*
411 * Disable the NS interrupt locally.
412 */
413 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
414 #endif
415 }
416
417
418 #if TSP_INIT_ASYNC
419 /* Save the Secure EL1 system register context */
420 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
421 cm_el1_sysregs_context_save(SECURE);
422
423 /* Program EL3 registers to enable entry into the next EL */
424 next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
425 assert(next_image_info);
426 assert(NON_SECURE ==
427 GET_SECURITY_STATE(next_image_info->h.attr));
428
429 cm_init_my_context(next_image_info);
430 cm_prepare_el3_exit(NON_SECURE);
431 SMC_RET0(cm_get_context(NON_SECURE));
432 #else
433 /*
434 * SP reports completion. The SPD must have initiated
435 * the original request through a synchronous entry
436 * into the SP. Jump back to the original C runtime
437 * context.
438 */
439 tspd_synchronous_sp_exit(tsp_ctx, x1);
440 break;
441 #endif
442 /*
443 * This function ID is used only by the SP to indicate it has finished
444 * aborting a preempted Yielding SMC Call.
445 */
446 case TSP_ABORT_DONE:
447
448 /*
449 * These function IDs are used only by the SP to indicate it has
450 * finished:
451 * 1. turning itself on in response to an earlier psci
452 * cpu_on request
453 * 2. resuming itself after an earlier psci cpu_suspend
454 * request.
455 */
456 case TSP_ON_DONE:
457 case TSP_RESUME_DONE:
458
459 /*
460 * These function IDs are used only by the SP to indicate it has
461 * finished:
462 * 1. suspending itself after an earlier psci cpu_suspend
463 * request.
464 * 2. turning itself off in response to an earlier psci
465 * cpu_off request.
466 */
467 case TSP_OFF_DONE:
468 case TSP_SUSPEND_DONE:
469 case TSP_SYSTEM_OFF_DONE:
470 case TSP_SYSTEM_RESET_DONE:
471 if (ns)
472 SMC_RET1(handle, SMC_UNK);
473
474 /*
475 * SP reports completion. The SPD must have initiated the
476 * original request through a synchronous entry into the SP.
477 * Jump back to the original C runtime context, and pass x1 as
478 * return value to the caller
479 */
480 tspd_synchronous_sp_exit(tsp_ctx, x1);
481 break;
482
483 /*
484 * Request from non-secure client to perform an
485 * arithmetic operation or response from secure
486 * payload to an earlier request.
487 */
488 case TSP_FAST_FID(TSP_ADD):
489 case TSP_FAST_FID(TSP_SUB):
490 case TSP_FAST_FID(TSP_MUL):
491 case TSP_FAST_FID(TSP_DIV):
492
493 case TSP_YIELD_FID(TSP_ADD):
494 case TSP_YIELD_FID(TSP_SUB):
495 case TSP_YIELD_FID(TSP_MUL):
496 case TSP_YIELD_FID(TSP_DIV):
497 if (ns) {
498 /*
499 * This is a fresh request from the non-secure client.
500 * The parameters are in x1 and x2. Figure out which
501 * registers need to be preserved, save the non-secure
502 * state and send the request to the secure payload.
503 */
504 assert(handle == cm_get_context(NON_SECURE));
505
506 /* Check if we are already preempted */
507 if (get_yield_smc_active_flag(tsp_ctx->state))
508 SMC_RET1(handle, SMC_UNK);
509
510 cm_el1_sysregs_context_save(NON_SECURE);
511
512 /* Save x1 and x2 for use by TSP_GET_ARGS call below */
513 store_tsp_args(tsp_ctx, x1, x2);
514
515 /*
516 * We are done stashing the non-secure context. Ask the
517 * secure payload to do the work now.
518 */
519
520 /*
521 * Verify if there is a valid context to use, copy the
522 * operation type and parameters to the secure context
523 * and jump to the fast smc entry point in the secure
524 * payload. Entry into S-EL1 will take place upon exit
525 * from this function.
526 */
527 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
528
529 /* Set appropriate entry for SMC.
530 * We expect the TSP to manage the PSTATE.I and PSTATE.F
531 * flags as appropriate.
532 */
533 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) {
534 cm_set_elr_el3(SECURE, (uint64_t)
535 &tsp_vectors->fast_smc_entry);
536 } else {
537 set_yield_smc_active_flag(tsp_ctx->state);
538 cm_set_elr_el3(SECURE, (uint64_t)
539 &tsp_vectors->yield_smc_entry);
540 #if TSP_NS_INTR_ASYNC_PREEMPT
541 /*
542 * Enable the routing of NS interrupts to EL3
543 * during processing of a Yielding SMC Call on
544 * this core.
545 */
546 enable_intr_rm_local(INTR_TYPE_NS, SECURE);
547 #endif
548
549 #if EL3_EXCEPTION_HANDLING
550 /*
551 * With EL3 exception handling, while an SMC is
552 * being processed, Non-secure interrupts can't
553 * preempt Secure execution. However, for
554 * yielding SMCs, we want preemption to happen;
555 * so explicitly allow NS preemption in this
556 * case, and supply the preemption return code
557 * for TSP.
558 */
559 ehf_allow_ns_preemption(TSP_PREEMPTED);
560 #endif
561 }
562
563 cm_el1_sysregs_context_restore(SECURE);
564 cm_set_next_eret_context(SECURE);
565 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2);
566 } else {
567 /*
568 * This is the result from the secure client of an
569 * earlier request. The results are in x1-x3. Copy it
570 * into the non-secure context, save the secure state
571 * and return to the non-secure state.
572 */
573 assert(handle == cm_get_context(SECURE));
574 cm_el1_sysregs_context_save(SECURE);
575
576 /* Get a reference to the non-secure context */
577 ns_cpu_context = cm_get_context(NON_SECURE);
578 assert(ns_cpu_context);
579
580 /* Restore non-secure state */
581 cm_el1_sysregs_context_restore(NON_SECURE);
582 cm_set_next_eret_context(NON_SECURE);
583 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_YIELD) {
584 clr_yield_smc_active_flag(tsp_ctx->state);
585 #if TSP_NS_INTR_ASYNC_PREEMPT
586 /*
587 * Disable the routing of NS interrupts to EL3
588 * after processing of a Yielding SMC Call on
589 * this core is finished.
590 */
591 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
592 #endif
593 }
594
595 SMC_RET3(ns_cpu_context, x1, x2, x3);
596 }
597 assert(0); /* Unreachable */
598
599 /*
600 * Request from the non-secure world to abort a preempted Yielding SMC
601 * Call.
602 */
603 case TSP_FID_ABORT:
604 /* ABORT should only be invoked by normal world */
605 if (!ns) {
606 assert(0);
607 break;
608 }
609
610 assert(handle == cm_get_context(NON_SECURE));
611 cm_el1_sysregs_context_save(NON_SECURE);
612
613 /* Abort the preempted SMC request */
614 if (!tspd_abort_preempted_smc(tsp_ctx)) {
615 /*
616 * If there was no preempted SMC to abort, return
617 * SMC_UNK.
618 *
619 * Restoring the NON_SECURE context is not necessary as
620 * the synchronous entry did not take place if the
621 * return code of tspd_abort_preempted_smc is zero.
622 */
623 cm_set_next_eret_context(NON_SECURE);
624 break;
625 }
626
627 cm_el1_sysregs_context_restore(NON_SECURE);
628 cm_set_next_eret_context(NON_SECURE);
629 SMC_RET1(handle, SMC_OK);
630
631 /*
632 * Request from non secure world to resume the preempted
633 * Yielding SMC Call.
634 */
635 case TSP_FID_RESUME:
636 /* RESUME should be invoked only by normal world */
637 if (!ns) {
638 assert(0);
639 break;
640 }
641
642 /*
643 * This is a resume request from the non-secure client.
644 * save the non-secure state and send the request to
645 * the secure payload.
646 */
647 assert(handle == cm_get_context(NON_SECURE));
648
649 /* Check if we are already preempted before resume */
650 if (!get_yield_smc_active_flag(tsp_ctx->state))
651 SMC_RET1(handle, SMC_UNK);
652
653 cm_el1_sysregs_context_save(NON_SECURE);
654
655 /*
656 * We are done stashing the non-secure context. Ask the
657 * secure payload to do the work now.
658 */
659 #if TSP_NS_INTR_ASYNC_PREEMPT
660 /*
661 * Enable the routing of NS interrupts to EL3 during resumption
662 * of a Yielding SMC Call on this core.
663 */
664 enable_intr_rm_local(INTR_TYPE_NS, SECURE);
665 #endif
666
667 #if EL3_EXCEPTION_HANDLING
668 /*
669 * Allow the resumed yielding SMC processing to be preempted by
670 * Non-secure interrupts. Also, supply the preemption return
671 * code for TSP.
672 */
673 ehf_allow_ns_preemption(TSP_PREEMPTED);
674 #endif
675
676 /* We just need to return to the preempted point in
677 * TSP and the execution will resume as normal.
678 */
679 cm_el1_sysregs_context_restore(SECURE);
680 cm_set_next_eret_context(SECURE);
681 SMC_RET0(&tsp_ctx->cpu_ctx);
682
683 /*
684 * This is a request from the secure payload for more arguments
685 * for an ongoing arithmetic operation requested by the
686 * non-secure world. Simply return the arguments from the non-
687 * secure client in the original call.
688 */
689 case TSP_GET_ARGS:
690 if (ns)
691 SMC_RET1(handle, SMC_UNK);
692
693 get_tsp_args(tsp_ctx, x1, x2);
694 SMC_RET2(handle, x1, x2);
695
696 case TOS_CALL_COUNT:
697 /*
698 * Return the number of service function IDs implemented to
699 * provide service to non-secure
700 */
701 SMC_RET1(handle, TSP_NUM_FID);
702
703 case TOS_UID:
704 /* Return TSP UID to the caller */
705 SMC_UUID_RET(handle, tsp_uuid);
706
707 case TOS_CALL_VERSION:
708 /* Return the version of current implementation */
709 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR);
710
711 default:
712 break;
713 }
714
715 SMC_RET1(handle, SMC_UNK);
716 }
717
718 /* Define a SPD runtime service descriptor for fast SMC calls */
719 DECLARE_RT_SVC(
720 tspd_fast,
721
722 OEN_TOS_START,
723 OEN_TOS_END,
724 SMC_TYPE_FAST,
725 tspd_setup,
726 tspd_smc_handler
727 );
728
729 /* Define a SPD runtime service descriptor for Yielding SMC Calls */
730 DECLARE_RT_SVC(
731 tspd_std,
732
733 OEN_TOS_START,
734 OEN_TOS_END,
735 SMC_TYPE_YIELD,
736 NULL,
737 tspd_smc_handler
738 );
739