1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	psci {
26		compatible = "arm,psci-1.0";
27		method = "smc";
28	};
29
30	intc: interrupt-controller@a0021000 {
31		compatible = "arm,cortex-a7-gic";
32		#interrupt-cells = <3>;
33		interrupt-controller;
34		reg = <0xa0021000 0x1000>,
35		      <0xa0022000 0x2000>;
36	};
37
38	clocks {
39		clk_hse: clk-hse {
40			#clock-cells = <0>;
41			compatible = "fixed-clock";
42			clock-frequency = <24000000>;
43		};
44
45		clk_hsi: clk-hsi {
46			#clock-cells = <0>;
47			compatible = "fixed-clock";
48			clock-frequency = <64000000>;
49		};
50
51		clk_lse: clk-lse {
52			#clock-cells = <0>;
53			compatible = "fixed-clock";
54			clock-frequency = <32768>;
55		};
56
57		clk_lsi: clk-lsi {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <32000>;
61		};
62
63		clk_csi: clk-csi {
64			#clock-cells = <0>;
65			compatible = "fixed-clock";
66			clock-frequency = <4000000>;
67		};
68	};
69
70	soc {
71		compatible = "simple-bus";
72		#address-cells = <1>;
73		#size-cells = <1>;
74		interrupt-parent = <&intc>;
75		ranges;
76
77		timers12: timer@40006000 {
78			#address-cells = <1>;
79			#size-cells = <0>;
80			compatible = "st,stm32-timers";
81			reg = <0x40006000 0x400>;
82			clocks = <&rcc TIM12_K>;
83			clock-names = "int";
84			status = "disabled";
85		};
86
87		usart2: serial@4000e000 {
88			compatible = "st,stm32h7-uart";
89			reg = <0x4000e000 0x400>;
90			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
91			clocks = <&rcc USART2_K>;
92			resets = <&rcc USART2_R>;
93			status = "disabled";
94		};
95
96		usart3: serial@4000f000 {
97			compatible = "st,stm32h7-uart";
98			reg = <0x4000f000 0x400>;
99			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
100			clocks = <&rcc USART3_K>;
101			resets = <&rcc USART3_R>;
102			status = "disabled";
103		};
104
105		uart4: serial@40010000 {
106			compatible = "st,stm32h7-uart";
107			reg = <0x40010000 0x400>;
108			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
109			clocks = <&rcc UART4_K>;
110			resets = <&rcc UART4_R>;
111			wakeup-source;
112			status = "disabled";
113		};
114
115		uart5: serial@40011000 {
116			compatible = "st,stm32h7-uart";
117			reg = <0x40011000 0x400>;
118			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
119			clocks = <&rcc UART5_K>;
120			resets = <&rcc UART5_R>;
121			status = "disabled";
122		};
123
124		uart7: serial@40018000 {
125			compatible = "st,stm32h7-uart";
126			reg = <0x40018000 0x400>;
127			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
128			clocks = <&rcc UART7_K>;
129			resets = <&rcc UART7_R>;
130			status = "disabled";
131		};
132
133		uart8: serial@40019000 {
134			compatible = "st,stm32h7-uart";
135			reg = <0x40019000 0x400>;
136			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
137			clocks = <&rcc UART8_K>;
138			resets = <&rcc UART8_R>;
139			status = "disabled";
140		};
141
142		usart6: serial@44003000 {
143			compatible = "st,stm32h7-uart";
144			reg = <0x44003000 0x400>;
145			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
146			clocks = <&rcc USART6_K>;
147			resets = <&rcc USART6_R>;
148			status = "disabled";
149		};
150
151		timers15: timer@44006000 {
152			#address-cells = <1>;
153			#size-cells = <0>;
154			compatible = "st,stm32-timers";
155			reg = <0x44006000 0x400>;
156			clocks = <&rcc TIM15_K>;
157			clock-names = "int";
158			status = "disabled";
159		};
160
161		usbotg_hs: usb-otg@49000000 {
162			compatible = "st,stm32mp1-hsotg", "snps,dwc2";
163			reg = <0x49000000 0x10000>;
164			clocks = <&rcc USBO_K>;
165			clock-names = "otg";
166			resets = <&rcc USBO_R>;
167			reset-names = "dwc2";
168			interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
169			g-rx-fifo-size = <512>;
170			g-np-tx-fifo-size = <32>;
171			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
172			dr_mode = "otg";
173			usb33d-supply = <&usb33>;
174			status = "disabled";
175		};
176
177		rcc: rcc@50000000 {
178			compatible = "st,stm32mp1-rcc", "syscon";
179			reg = <0x50000000 0x1000>;
180			#address-cells = <1>;
181			#size-cells = <0>;
182			#clock-cells = <1>;
183			#reset-cells = <1>;
184			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
185			secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
186			secure-interrupt-names = "wakeup";
187		};
188
189		pwr_regulators: pwr@50001000 {
190			compatible = "st,stm32mp1,pwr-reg";
191			reg = <0x50001000 0x10>;
192			st,tzcr = <&rcc 0x0 0x1>;
193
194			reg11: reg11 {
195				regulator-name = "reg11";
196				regulator-min-microvolt = <1100000>;
197				regulator-max-microvolt = <1100000>;
198			};
199
200			reg18: reg18 {
201				regulator-name = "reg18";
202				regulator-min-microvolt = <1800000>;
203				regulator-max-microvolt = <1800000>;
204			};
205
206			usb33: usb33 {
207				regulator-name = "usb33";
208				regulator-min-microvolt = <3300000>;
209				regulator-max-microvolt = <3300000>;
210			};
211		};
212
213		pwr_mcu: pwr_mcu@50001014 {
214			compatible = "st,stm32mp151-pwr-mcu", "syscon";
215			reg = <0x50001014 0x4>;
216		};
217
218		pwr_irq: pwr@50001020 {
219			compatible = "st,stm32mp1-pwr";
220			reg = <0x50001020 0x100>;
221			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
222			interrupt-controller;
223			#interrupt-cells = <3>;
224		};
225
226		exti: interrupt-controller@5000d000 {
227			compatible = "st,stm32mp1-exti", "syscon";
228			interrupt-controller;
229			#interrupt-cells = <2>;
230			reg = <0x5000d000 0x400>;
231
232			/* exti_pwr is an extra interrupt controller used for
233			 * EXTI 55 to 60. It's mapped on pwr interrupt
234			 * controller.
235			 */
236			exti_pwr: exti-pwr {
237				interrupt-controller;
238				#interrupt-cells = <2>;
239				interrupt-parent = <&pwr_irq>;
240				st,irq-number = <6>;
241			};
242		};
243
244		syscfg: syscon@50020000 {
245			compatible = "st,stm32mp157-syscfg", "syscon";
246			reg = <0x50020000 0x400>;
247			clocks = <&rcc SYSCFG>;
248		};
249
250		hash1: hash@54002000 {
251			compatible = "st,stm32f756-hash";
252			reg = <0x54002000 0x400>;
253			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
254			clocks = <&rcc HASH1>;
255			resets = <&rcc HASH1_R>;
256			status = "disabled";
257		};
258
259		rng1: rng@54003000 {
260			compatible = "st,stm32-rng";
261			reg = <0x54003000 0x400>;
262			clocks = <&rcc RNG1_K>;
263			resets = <&rcc RNG1_R>;
264			status = "disabled";
265		};
266
267		fmc: memory-controller@58002000 {
268			#address-cells = <2>;
269			#size-cells = <1>;
270			compatible = "st,stm32mp1-fmc2-ebi";
271			reg = <0x58002000 0x1000>;
272			clocks = <&rcc FMC_K>;
273			resets = <&rcc FMC_R>;
274			status = "disabled";
275
276			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
277				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
278				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
279				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
280				 <4 0 0x80000000 0x10000000>; /* NAND */
281
282			nand-controller@4,0 {
283				#address-cells = <1>;
284				#size-cells = <0>;
285				compatible = "st,stm32mp1-fmc2-nfc";
286				reg = <4 0x00000000 0x1000>,
287				      <4 0x08010000 0x1000>,
288				      <4 0x08020000 0x1000>,
289				      <4 0x01000000 0x1000>,
290				      <4 0x09010000 0x1000>,
291				      <4 0x09020000 0x1000>;
292				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
293				status = "disabled";
294			};
295		};
296
297		qspi: spi@58003000 {
298			compatible = "st,stm32f469-qspi";
299			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
300			reg-names = "qspi", "qspi_mm";
301			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
302			clocks = <&rcc QSPI_K>;
303			resets = <&rcc QSPI_R>;
304			status = "disabled";
305		};
306
307		sdmmc1: sdmmc@58005000 {
308			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
309			arm,primecell-periphid = <0x00253180>;
310			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
311			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
312			interrupt-names = "cmd_irq";
313			clocks = <&rcc SDMMC1_K>;
314			clock-names = "apb_pclk";
315			resets = <&rcc SDMMC1_R>;
316			cap-sd-highspeed;
317			cap-mmc-highspeed;
318			max-frequency = <120000000>;
319			status = "disabled";
320		};
321
322		sdmmc2: sdmmc@58007000 {
323			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
324			arm,primecell-periphid = <0x00253180>;
325			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
326			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
327			interrupt-names = "cmd_irq";
328			clocks = <&rcc SDMMC2_K>;
329			clock-names = "apb_pclk";
330			resets = <&rcc SDMMC2_R>;
331			cap-sd-highspeed;
332			cap-mmc-highspeed;
333			max-frequency = <120000000>;
334			status = "disabled";
335		};
336
337		iwdg2: watchdog@5a002000 {
338			compatible = "st,stm32mp1-iwdg";
339			reg = <0x5a002000 0x400>;
340			secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
341			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
342			clock-names = "pclk", "lsi";
343			status = "disabled";
344		};
345
346		usbphyc: usbphyc@5a006000 {
347			#address-cells = <1>;
348			#size-cells = <0>;
349			#clock-cells = <0>;
350			compatible = "st,stm32mp1-usbphyc";
351			reg = <0x5a006000 0x1000>;
352			clocks = <&rcc USBPHY_K>;
353			resets = <&rcc USBPHY_R>;
354			vdda1v1-supply = <&reg11>;
355			vdda1v8-supply = <&reg18>;
356			status = "disabled";
357
358			usbphyc_port0: usb-phy@0 {
359				#phy-cells = <0>;
360				reg = <0>;
361			};
362
363			usbphyc_port1: usb-phy@1 {
364				#phy-cells = <1>;
365				reg = <1>;
366			};
367		};
368
369		usart1: serial@5c000000 {
370			compatible = "st,stm32h7-uart";
371			reg = <0x5c000000 0x400>;
372			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
373			clocks = <&rcc USART1_K>;
374			resets = <&rcc USART1_R>;
375			status = "disabled";
376		};
377
378		spi6: spi@5c001000 {
379			#address-cells = <1>;
380			#size-cells = <0>;
381			compatible = "st,stm32h7-spi";
382			reg = <0x5c001000 0x400>;
383			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
384			clocks = <&rcc SPI6_K>;
385			resets = <&rcc SPI6_R>;
386			status = "disabled";
387		};
388
389		i2c4: i2c@5c002000 {
390			compatible = "st,stm32mp15-i2c";
391			reg = <0x5c002000 0x400>;
392			interrupt-names = "event", "error";
393			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
394					      <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
395			clocks = <&rcc I2C4_K>;
396			resets = <&rcc I2C4_R>;
397			#address-cells = <1>;
398			#size-cells = <0>;
399			st,syscfg-fmp = <&syscfg 0x4 0x8>;
400			wakeup-source;
401			status = "disabled";
402		};
403
404		iwdg1: watchdog@5c003000 {
405			compatible = "st,stm32mp1-iwdg";
406			reg = <0x5C003000 0x400>;
407			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
408			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
409			clock-names = "pclk", "lsi";
410			status = "disabled";
411		};
412
413		rtc: rtc@5c004000 {
414			compatible = "st,stm32mp1-rtc";
415			reg = <0x5c004000 0x400>;
416			clocks = <&rcc RTCAPB>, <&rcc RTC>;
417			clock-names = "pclk", "rtc_ck";
418			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
419			status = "disabled";
420		};
421
422		bsec: nvmem@5c005000 {
423			compatible = "st,stm32mp15-bsec";
424			reg = <0x5c005000 0x400>;
425			#address-cells = <1>;
426			#size-cells = <1>;
427			ts_cal1: calib@5c {
428				reg = <0x5c 0x2>;
429			};
430			ts_cal2: calib@5e {
431				reg = <0x5e 0x2>;
432			};
433		};
434
435		etzpc: etzpc@5c007000 {
436			compatible = "st,stm32-etzpc";
437			reg = <0x5C007000 0x400>;
438			clocks = <&rcc TZPC>;
439			status = "disabled";
440			secure-status = "okay";
441		};
442
443		stgen: stgen@5c008000 {
444			compatible = "st,stm32-stgen";
445			reg = <0x5C008000 0x1000>;
446		};
447
448		i2c6: i2c@5c009000 {
449			compatible = "st,stm32mp15-i2c";
450			reg = <0x5c009000 0x400>;
451			interrupt-names = "event", "error";
452			interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
453					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
454			clocks = <&rcc I2C6_K>;
455			resets = <&rcc I2C6_R>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458			st,syscfg-fmp = <&syscfg 0x4 0x20>;
459			wakeup-source;
460			status = "disabled";
461		};
462
463		tamp: tamp@5c00a000 {
464			compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
465			reg = <0x5c00a000 0x400>;
466			secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
467			clocks = <&rcc RTCAPB>;
468		};
469
470		/*
471		 * Break node order to solve dependency probe issue between
472		 * pinctrl and exti.
473		 */
474		pinctrl: pin-controller@50002000 {
475			#address-cells = <1>;
476			#size-cells = <1>;
477			compatible = "st,stm32mp157-pinctrl";
478			ranges = <0 0x50002000 0xa400>;
479			interrupt-parent = <&exti>;
480			st,syscfg = <&exti 0x60 0xff>;
481			pins-are-numbered;
482
483			gpioa: gpio@50002000 {
484				gpio-controller;
485				#gpio-cells = <2>;
486				interrupt-controller;
487				#interrupt-cells = <2>;
488				reg = <0x0 0x400>;
489				clocks = <&rcc GPIOA>;
490				st,bank-name = "GPIOA";
491				status = "disabled";
492			};
493
494			gpiob: gpio@50003000 {
495				gpio-controller;
496				#gpio-cells = <2>;
497				interrupt-controller;
498				#interrupt-cells = <2>;
499				reg = <0x1000 0x400>;
500				clocks = <&rcc GPIOB>;
501				st,bank-name = "GPIOB";
502				status = "disabled";
503			};
504
505			gpioc: gpio@50004000 {
506				gpio-controller;
507				#gpio-cells = <2>;
508				interrupt-controller;
509				#interrupt-cells = <2>;
510				reg = <0x2000 0x400>;
511				clocks = <&rcc GPIOC>;
512				st,bank-name = "GPIOC";
513				status = "disabled";
514			};
515
516			gpiod: gpio@50005000 {
517				gpio-controller;
518				#gpio-cells = <2>;
519				interrupt-controller;
520				#interrupt-cells = <2>;
521				reg = <0x3000 0x400>;
522				clocks = <&rcc GPIOD>;
523				st,bank-name = "GPIOD";
524				status = "disabled";
525			};
526
527			gpioe: gpio@50006000 {
528				gpio-controller;
529				#gpio-cells = <2>;
530				interrupt-controller;
531				#interrupt-cells = <2>;
532				reg = <0x4000 0x400>;
533				clocks = <&rcc GPIOE>;
534				st,bank-name = "GPIOE";
535				status = "disabled";
536			};
537
538			gpiof: gpio@50007000 {
539				gpio-controller;
540				#gpio-cells = <2>;
541				interrupt-controller;
542				#interrupt-cells = <2>;
543				reg = <0x5000 0x400>;
544				clocks = <&rcc GPIOF>;
545				st,bank-name = "GPIOF";
546				status = "disabled";
547			};
548
549			gpiog: gpio@50008000 {
550				gpio-controller;
551				#gpio-cells = <2>;
552				interrupt-controller;
553				#interrupt-cells = <2>;
554				reg = <0x6000 0x400>;
555				clocks = <&rcc GPIOG>;
556				st,bank-name = "GPIOG";
557				status = "disabled";
558			};
559
560			gpioh: gpio@50009000 {
561				gpio-controller;
562				#gpio-cells = <2>;
563				interrupt-controller;
564				#interrupt-cells = <2>;
565				reg = <0x7000 0x400>;
566				clocks = <&rcc GPIOH>;
567				st,bank-name = "GPIOH";
568				status = "disabled";
569			};
570
571			gpioi: gpio@5000a000 {
572				gpio-controller;
573				#gpio-cells = <2>;
574				interrupt-controller;
575				#interrupt-cells = <2>;
576				reg = <0x8000 0x400>;
577				clocks = <&rcc GPIOI>;
578				st,bank-name = "GPIOI";
579				status = "disabled";
580			};
581
582			gpioj: gpio@5000b000 {
583				gpio-controller;
584				#gpio-cells = <2>;
585				interrupt-controller;
586				#interrupt-cells = <2>;
587				reg = <0x9000 0x400>;
588				clocks = <&rcc GPIOJ>;
589				st,bank-name = "GPIOJ";
590				status = "disabled";
591			};
592
593			gpiok: gpio@5000c000 {
594				gpio-controller;
595				#gpio-cells = <2>;
596				interrupt-controller;
597				#interrupt-cells = <2>;
598				reg = <0xa000 0x400>;
599				clocks = <&rcc GPIOK>;
600				st,bank-name = "GPIOK";
601				status = "disabled";
602			};
603		};
604
605		pinctrl_z: pin-controller-z@54004000 {
606			#address-cells = <1>;
607			#size-cells = <1>;
608			compatible = "st,stm32mp157-z-pinctrl";
609			ranges = <0 0x54004000 0x400>;
610			pins-are-numbered;
611			interrupt-parent = <&exti>;
612			st,syscfg = <&exti 0x60 0xff>;
613
614			gpioz: gpio@54004000 {
615				gpio-controller;
616				#gpio-cells = <2>;
617				interrupt-controller;
618				#interrupt-cells = <2>;
619				reg = <0 0x400>;
620				clocks = <&rcc GPIOZ>;
621				st,bank-name = "GPIOZ";
622				st,bank-ioport = <11>;
623				status = "disabled";
624			};
625		};
626	};
627};
628