1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9
10 static csh handle;
11
12 struct platform {
13 cs_arch arch;
14 cs_mode mode;
15 unsigned char *code;
16 size_t size;
17 const char *comment;
18 int syntax;
19 };
20
print_string_hex(const char * comment,unsigned char * str,size_t len)21 static void print_string_hex(const char *comment, unsigned char *str, size_t len)
22 {
23 unsigned char *c;
24
25 printf("%s", comment);
26 for (c = str; c < str + len; c++) {
27 printf("0x%02x ", *c & 0xff);
28 }
29
30 printf("\n");
31 }
32
print_insn_detail(csh cs_handle,cs_insn * ins)33 static void print_insn_detail(csh cs_handle, cs_insn *ins)
34 {
35 cs_arm *arm;
36 int i;
37 cs_regs regs_read, regs_write;
38 uint8_t regs_read_count, regs_write_count;
39
40 // detail can be NULL on "data" instruction if SKIPDATA option is turned ON
41 if (ins->detail == NULL)
42 return;
43
44 arm = &(ins->detail->arm);
45
46 if (arm->op_count)
47 printf("\top_count: %u\n", arm->op_count);
48
49 for (i = 0; i < arm->op_count; i++) {
50 cs_arm_op *op = &(arm->operands[i]);
51 switch((int)op->type) {
52 default:
53 break;
54 case ARM_OP_REG:
55 printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(cs_handle, op->reg));
56 break;
57 case ARM_OP_IMM:
58 printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
59 break;
60 case ARM_OP_FP:
61 #if defined(_KERNEL_MODE)
62 // Issue #681: Windows kernel does not support formatting float point
63 printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
64 #else
65 printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
66 #endif
67 break;
68 case ARM_OP_MEM:
69 printf("\t\toperands[%u].type: MEM\n", i);
70 if (op->mem.base != ARM_REG_INVALID)
71 printf("\t\t\toperands[%u].mem.base: REG = %s\n",
72 i, cs_reg_name(cs_handle, op->mem.base));
73 if (op->mem.index != ARM_REG_INVALID)
74 printf("\t\t\toperands[%u].mem.index: REG = %s\n",
75 i, cs_reg_name(cs_handle, op->mem.index));
76 if (op->mem.scale != 1)
77 printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
78 if (op->mem.disp != 0)
79 printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
80 if (op->mem.lshift != 0)
81 printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift);
82
83 break;
84 case ARM_OP_PIMM:
85 printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm);
86 break;
87 case ARM_OP_CIMM:
88 printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm);
89 break;
90 case ARM_OP_SETEND:
91 printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le");
92 break;
93 case ARM_OP_SYSREG:
94 printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg);
95 break;
96 }
97
98 if (op->neon_lane != -1) {
99 printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane);
100 }
101
102 switch(op->access) {
103 default:
104 break;
105 case CS_AC_READ:
106 printf("\t\toperands[%u].access: READ\n", i);
107 break;
108 case CS_AC_WRITE:
109 printf("\t\toperands[%u].access: WRITE\n", i);
110 break;
111 case CS_AC_READ | CS_AC_WRITE:
112 printf("\t\toperands[%u].access: READ | WRITE\n", i);
113 break;
114 }
115
116 if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
117 if (op->shift.type < ARM_SFT_ASR_REG)
118 // shift with constant value
119 printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value);
120 else
121 // shift with register
122 printf("\t\t\tShift: %u = %s\n", op->shift.type,
123 cs_reg_name(cs_handle, op->shift.value));
124 }
125
126 if (op->vector_index != -1) {
127 printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index);
128 }
129
130 if (op->subtracted)
131 printf("\t\tSubtracted: True\n");
132 }
133
134 if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
135 printf("\tCode condition: %u\n", arm->cc);
136
137 if (arm->update_flags)
138 printf("\tUpdate-flags: True\n");
139
140 if (arm->writeback)
141 printf("\tWrite-back: True\n");
142
143 if (arm->cps_mode)
144 printf("\tCPSI-mode: %u\n", arm->cps_mode);
145
146 if (arm->cps_flag)
147 printf("\tCPSI-flag: %u\n", arm->cps_flag);
148
149 if (arm->vector_data)
150 printf("\tVector-data: %u\n", arm->vector_data);
151
152 if (arm->vector_size)
153 printf("\tVector-size: %u\n", arm->vector_size);
154
155 if (arm->usermode)
156 printf("\tUser-mode: True\n");
157
158 if (arm->mem_barrier)
159 printf("\tMemory-barrier: %u\n", arm->mem_barrier);
160
161 // Print out all registers accessed by this instruction (either implicit or explicit)
162 if (!cs_regs_access(cs_handle, ins,
163 regs_read, ®s_read_count,
164 regs_write, ®s_write_count)) {
165 if (regs_read_count) {
166 printf("\tRegisters read:");
167 for(i = 0; i < regs_read_count; i++) {
168 printf(" %s", cs_reg_name(cs_handle, regs_read[i]));
169 }
170 printf("\n");
171 }
172
173 if (regs_write_count) {
174 printf("\tRegisters modified:");
175 for(i = 0; i < regs_write_count; i++) {
176 printf(" %s", cs_reg_name(cs_handle, regs_write[i]));
177 }
178 printf("\n");
179 }
180 }
181
182 printf("\n");
183 }
184
test()185 static void test()
186 {
187 //#define ARM_CODE "\x04\xe0\x2d\xe5" // str lr, [sp, #-0x4]!
188 //#define ARM_CODE "\xe0\x83\x22\xe5" // str r8, [r2, #-0x3e0]!
189 //#define ARM_CODE "\xf1\x02\x03\x0e" // mcreq p0x2, #0x0, r0, c0x3, c0x1, #0x7
190 //#define ARM_CODE "\x00\x00\xa0\xe3" // mov r0, #0x0
191 //#define ARM_CODE "\x02\x30\xc1\xe7" // strb r3, [r1, r2]
192 //#define ARM_CODE "\x00\x00\x53\xe3" // cmp r3, #0x0
193 //#define ARM_CODE "\x02\x00\xa1\xe2" // adc r0, r1, r2
194 //#define ARM_CODE "\x21\x01\xa0\xe0" // adc r0, r0, r1, lsr #2
195 //#define ARM_CODE "\x21\x01\xb0\xe0" // adcs r0, r0, r1, lsr #2
196 //#define ARM_CODE "\x32\x03\xa1\xe0" // adc r0, r1, r2, lsr r3
197 //#define ARM_CODE "\x22\x01\xa1\xe0" // adc r0, r1, r2, lsr #2
198 //#define ARM_CODE "\x65\x61\x4f\x50" // subpl r6, pc, r5, ror #2
199 //#define ARM_CODE "\x30\x30\x53\xe5" // ldrb r3, [r3, #-0x30]
200 //#define ARM_CODE "\xb6\x10\xdf\xe1" // ldrh r1, [pc, #0x6]
201 //#define ARM_CODE "\x02\x00\x9f\xef" // svc #0x9f0002
202 //#define ARM_CODE "\x00\xc0\x27\xea" // b 0x9F0002: FIXME: disasm as "b #0x9f0000"
203 //#define ARM_CODE "\x12\x13\xa0\xe1" // lsl r1, r2, r3
204 //#define ARM_CODE "\x82\x11\xa0\xe1" // lsl r1, r2, #0x3
205 //#define ARM_CODE "\x00\xc0\xa0\xe1" // mov ip, r0
206 //#define ARM_CODE "\x02\x00\x12\xe3" // tst r2, #2
207 //#define ARM_CODE "\x51\x12\xa0\xe1" // asr r1, r2
208 //#define ARM_CODE "\x72\x10\xef\xe6" // uxtb r1, r2
209 //#define ARM_CODE "\xe0\x0a\xb7\xee" // vcvt.f64.f32 d0, s1
210 //#define ARM_CODE "\x9f\x0f\x91\xe1" // ldrex r0, [r1]
211 //#define ARM_CODE "\x0f\x06\x20\xf4" // vld1.8 {d0, d1, d2}, [r0]
212 //#define ARM_CODE "\x72\x00\xa1\xe6" // sxtab r0, r1, r2
213 //#define ARM_CODE "\x50\x06\x84\xf2" // vmov.i32 q0, #0x40000000
214 //#define ARM_CODE "\x73\xe0\xb8\xee" // mrc p0, #5, lr, c8, c3, #3
215 //#define ARM_CODE "\x12\x02\x81\xe6" // pkhbt r0, r1, r2, lsl #0x4
216 //#define ARM_CODE "\x12\x00\xa0\xe6" // ssat r0, #0x1, r2
217 //#define ARM_CODE "\x03\x60\x2d\xe9" // push {r0, r1, sp, lr}
218 //#define ARM_CODE "\x8f\x40\x60\xf4" // vld4.32 {d20, d21, d22, d23}, [r0]
219 //#define ARM_CODE "\xd0\x00\xc2\xe1" // ldrd r0, r1, [r2]
220 //#define ARM_CODE "\x08\xf0\xd0\xf5" // pld [r0, #0x8]
221 //#define ARM_CODE "\x10\x8b\xbc\xec" // ldc p11, c8, [r12], #64
222 //#define ARM_CODE "\xd4\x30\xd2\xe1" // ldrsb r3, [r2, #0x4]
223 //#define ARM_CODE "\x11\x0f\xbe\xf2" // vcvt.s32.f32 d0, d1, #2
224 //#define ARM_CODE "\x01\x01\x70\xe1" // cmn r0, r1, lsl #2
225 //#define ARM_CODE "\x06\x00\x91\xe2" // adds r0, r1, #6
226 //#define ARM_CODE "\x5b\xf0\x7f\xf5" // dmb ish
227 //#define ARM_CODE "\xf7\xff\xff\xfe"
228 //#define ARM_CODE "\x00\x20\xbd\xe8" // ldm sp!, {sp}
229 //#define ARM_CODE "\x00\xa0\xbd\xe8" // pop {sp, pc}
230 //#define ARM_CODE "\x90\x04\x0E\x00" // muleq lr, r0, r4
231 //#define ARM_CODE "\x90\x24\x0E\x00" // muleq lr, r0, r4
232 //#define ARM_CODE "\xb6\x10\x5f\xe1" // ldrh r1, [pc, #-6]
233
234 #define ARM_CODE "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
235
236 //#define ARM_CODE "\x86\x48\x60\xf4"
237
238 //#define ARM_CODE2 "\xf0\x24"
239 //#define ARM_CODE2 "\x83\xb0"
240 #define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
241 //#define THUMB_CODE "\x70\x47" // bl 0x26
242 //#define THUMB_CODE "\x07\xdd" // ble 0x1c
243 //#define THUMB_CODE "\x00\x47" // bx r0
244 //#define THUMB_CODE "\x01\x47" // bx r0
245 //#define THUMB_CODE "\x02\x47" // bx r0
246 //#define THUMB_CODE "\x0a\xbf" // itet eq
247
248 #define THUMB_CODE "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
249 //#define THUMB_CODE "\xe0\xf9\x4f\x07"
250
251 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
252 #define THUMB_MCLASS "\xef\xf3\x02\x80"
253 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
254
255 struct platform platforms[] = {
256 {
257 CS_ARCH_ARM,
258 CS_MODE_ARM,
259 (unsigned char *)ARM_CODE,
260 sizeof(ARM_CODE) - 1,
261 "ARM"
262 },
263 {
264 CS_ARCH_ARM,
265 CS_MODE_THUMB,
266 (unsigned char *)THUMB_CODE,
267 sizeof(THUMB_CODE) - 1,
268 "Thumb"
269 },
270 {
271 CS_ARCH_ARM,
272 CS_MODE_THUMB,
273 (unsigned char *)ARM_CODE2,
274 sizeof(ARM_CODE2) - 1,
275 "Thumb-mixed"
276 },
277 {
278 CS_ARCH_ARM,
279 CS_MODE_THUMB,
280 (unsigned char *)THUMB_CODE2,
281 sizeof(THUMB_CODE2) - 1,
282 "Thumb-2 & register named with numbers",
283 CS_OPT_SYNTAX_NOREGNAME
284 },
285 {
286 CS_ARCH_ARM,
287 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
288 (unsigned char*)THUMB_MCLASS,
289 sizeof(THUMB_MCLASS) - 1,
290 "Thumb-MClass"
291 },
292 {
293 CS_ARCH_ARM,
294 (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
295 (unsigned char*)ARMV8,
296 sizeof(ARMV8) - 1,
297 "Arm-V8"
298 },
299 };
300
301 uint64_t address = 0x80001000;
302 cs_insn *insn;
303 int i;
304 size_t count;
305
306 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
307 cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
308 if (err) {
309 printf("Failed on cs_open() with error returned: %u\n", err);
310 abort();
311 }
312
313 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
314
315 if (platforms[i].syntax)
316 cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax);
317
318 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
319 if (count) {
320 size_t j;
321 printf("****************\n");
322 printf("Platform: %s\n", platforms[i].comment);
323 print_string_hex("Code:", platforms[i].code, platforms[i].size);
324 printf("Disasm:\n");
325
326 for (j = 0; j < count; j++) {
327 printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
328 print_insn_detail(handle, &insn[j]);
329 }
330 printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
331
332 // free memory allocated by cs_disasm()
333 cs_free(insn, count);
334 } else {
335 printf("****************\n");
336 printf("Platform: %s\n", platforms[i].comment);
337 print_string_hex("Code:", platforms[i].code, platforms[i].size);
338 printf("ERROR: Failed to disasm given code!\n");
339 abort();
340 }
341
342 printf("\n");
343
344 cs_close(&handle);
345 }
346 }
347
main()348 int main()
349 {
350 test();
351
352 return 0;
353 }
354
355