1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 /** @file gem_exec_suspend.c
26 *
27 * Exercise executing batches across suspend before checking the results.
28 */
29
30 #include "igt.h"
31 #include "igt_gt.h"
32 #include "igt_dummyload.h"
33
34 #define NOSLEEP 0
35 #define SUSPEND_DEVICES 1
36 #define SUSPEND 2
37 #define HIBERNATE_DEVICES 3
38 #define HIBERNATE 4
39 #define mode(x) ((x) & 0xff)
40
41 #define LOCAL_I915_EXEC_BSD_SHIFT (13)
42 #define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
43
44 #define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
45
46 #define UNCACHED (0<<8)
47 #define CACHED (1<<8)
48 #define HANG (2<<8)
49
50 static void run_test(int fd, unsigned ring, unsigned flags);
51
check_bo(int fd,uint32_t handle)52 static void check_bo(int fd, uint32_t handle)
53 {
54 uint32_t *map;
55 int i;
56
57 igt_debug("Verifying result\n");
58 map = gem_mmap__cpu(fd, handle, 0, 4096, PROT_READ);
59 gem_set_domain(fd, handle, I915_GEM_DOMAIN_CPU, 0);
60 for (i = 0; i < 1024; i++)
61 igt_assert_eq(map[i], i);
62 munmap(map, 4096);
63 }
64
test_all(int fd,unsigned flags)65 static void test_all(int fd, unsigned flags)
66 {
67 unsigned engine;
68
69 for_each_physical_engine(fd, engine)
70 if (gem_can_store_dword(fd, engine))
71 run_test(fd, engine, flags & ~0xff);
72 }
73
has_semaphores(int fd)74 static bool has_semaphores(int fd)
75 {
76 struct drm_i915_getparam gp;
77 int val = -1;
78
79 memset(&gp, 0, sizeof(gp));
80 gp.param = I915_PARAM_HAS_SEMAPHORES;
81 gp.value = &val;
82
83 drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
84 errno = 0;
85
86 return val > 0;
87 }
88
run_test(int fd,unsigned engine,unsigned flags)89 static void run_test(int fd, unsigned engine, unsigned flags)
90 {
91 const int gen = intel_gen(intel_get_drm_devid(fd));
92 const uint32_t bbe = MI_BATCH_BUFFER_END;
93 struct drm_i915_gem_exec_object2 obj[2];
94 struct drm_i915_gem_relocation_entry reloc;
95 struct drm_i915_gem_execbuffer2 execbuf;
96 unsigned engines[16];
97 unsigned nengine;
98 igt_spin_t *spin = NULL;
99
100 nengine = 0;
101 if (engine == ALL_ENGINES) {
102 /* If we don't have semaphores, then every ring switch
103 * will result in a CPU stall until the previous write
104 * has finished. This is likely to hide any issue with
105 * the GPU being active across the suspend (because the
106 * GPU is then unlikely to be active!)
107 */
108 if (has_semaphores(fd)) {
109 for_each_physical_engine(fd, engine) {
110 if (gem_can_store_dword(fd, engine))
111 engines[nengine++] = engine;
112 }
113 } else {
114 igt_require(gem_has_ring(fd, 0));
115 igt_require(gem_can_store_dword(fd, 0));
116 engines[nengine++] = 0;
117 }
118 } else {
119 igt_require(gem_has_ring(fd, engine));
120 igt_require(gem_can_store_dword(fd, engine));
121 engines[nengine++] = engine;
122 }
123 igt_require(nengine);
124
125 /* Before suspending, check normal operation */
126 if (mode(flags) != NOSLEEP)
127 test_all(fd, flags);
128
129 gem_quiescent_gpu(fd);
130
131 memset(&execbuf, 0, sizeof(execbuf));
132 execbuf.buffers_ptr = to_user_pointer(obj);
133 execbuf.buffer_count = 2;
134 execbuf.flags = 1 << 11;
135 if (gen < 6)
136 execbuf.flags |= I915_EXEC_SECURE;
137
138 memset(obj, 0, sizeof(obj));
139 obj[0].handle = gem_create(fd, 4096);
140 gem_set_caching(fd, obj[0].handle, !!(flags & CACHED));
141 obj[0].flags |= EXEC_OBJECT_WRITE;
142 obj[1].handle = gem_create(fd, 4096);
143 gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
144 igt_require(__gem_execbuf(fd, &execbuf) == 0);
145 gem_close(fd, obj[1].handle);
146
147 memset(&reloc, 0, sizeof(reloc));
148 reloc.target_handle = obj[0].handle;
149 reloc.presumed_offset = obj[0].offset;
150 reloc.offset = sizeof(uint32_t);
151 if (gen >= 4 && gen < 8)
152 reloc.offset += sizeof(uint32_t);
153 reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
154 reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
155
156 obj[1].relocs_ptr = to_user_pointer(&reloc);
157 obj[1].relocation_count = 1;
158
159 for (int i = 0; i < 1024; i++) {
160 uint64_t offset;
161 uint32_t buf[16];
162 int b;
163
164 obj[1].handle = gem_create(fd, 4096);
165
166 reloc.delta = i * sizeof(uint32_t);
167 offset = reloc.presumed_offset + reloc.delta;
168
169 b = 0;
170 buf[b] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
171 if (gen >= 8) {
172 buf[++b] = offset;
173 buf[++b] = offset >> 32;
174 } else if (gen >= 4) {
175 buf[++b] = 0;
176 buf[++b] = offset;
177 } else {
178 buf[b] -= 1;
179 buf[++b] = offset;
180 }
181 buf[++b] = i;
182 buf[++b] = MI_BATCH_BUFFER_END;
183 gem_write(fd, obj[1].handle,
184 4096-sizeof(buf), buf, sizeof(buf));
185 execbuf.flags &= ~ENGINE_MASK;
186 execbuf.flags |= engines[rand() % nengine];
187 gem_execbuf(fd, &execbuf);
188 gem_close(fd, obj[1].handle);
189 }
190
191 if (flags & HANG)
192 spin = igt_spin_new(fd, .engine = engine);
193
194 switch (mode(flags)) {
195 case NOSLEEP:
196 break;
197
198 case SUSPEND_DEVICES:
199 igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
200 SUSPEND_TEST_DEVICES);
201 break;
202
203 case SUSPEND:
204 igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
205 SUSPEND_TEST_NONE);
206 break;
207
208 case HIBERNATE_DEVICES:
209 igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
210 SUSPEND_TEST_DEVICES);
211 break;
212
213 case HIBERNATE:
214 igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
215 SUSPEND_TEST_NONE);
216 break;
217 }
218
219 igt_spin_free(fd, spin);
220
221 check_bo(fd, obj[0].handle);
222 gem_close(fd, obj[0].handle);
223
224 gem_quiescent_gpu(fd);
225
226 /* After resume, make sure it still works */
227 if (mode(flags) != NOSLEEP)
228 test_all(fd, flags);
229 }
230
231 igt_main
232 {
233 const struct {
234 const char *suffix;
235 unsigned mode;
236 } modes[] = {
237 { "", NOSLEEP },
238 { "-S3", SUSPEND },
239 { "-S4", HIBERNATE },
240 { NULL, 0 }
241 }, *m;
242 const struct intel_execution_engine *e;
243 igt_hang_t hang;
244 int fd;
245
246 igt_skip_on_simulation();
247
248 igt_fixture {
249 fd = drm_open_driver_master(DRIVER_INTEL);
250 igt_require_gem(fd);
251 igt_require(gem_can_store_dword(fd, 0));
252
253 igt_fork_hang_detector(fd);
254 }
255
256 igt_subtest("basic")
257 run_test(fd, ALL_ENGINES, NOSLEEP);
258 igt_subtest("basic-S3-devices")
259 run_test(fd, ALL_ENGINES, SUSPEND_DEVICES);
260 igt_subtest("basic-S3")
261 run_test(fd, ALL_ENGINES, SUSPEND);
262 igt_subtest("basic-S4-devices")
263 run_test(fd, ALL_ENGINES, HIBERNATE_DEVICES);
264 igt_subtest("basic-S4")
265 run_test(fd, ALL_ENGINES, HIBERNATE);
266
267 for (e = intel_execution_engines; e->name; e++) {
268 for (m = modes; m->suffix; m++) {
269 igt_subtest_f("%s-uncached%s", e->name, m->suffix)
270 run_test(fd, e->exec_id | e->flags,
271 m->mode | UNCACHED);
272 igt_subtest_f("%s-cached%s", e->name, m->suffix)
273 run_test(fd, e->exec_id | e->flags,
274 m->mode | CACHED);
275 }
276 }
277
278 igt_fixture {
279 igt_stop_hang_detector();
280 hang = igt_allow_hang(fd, 0, 0);
281 }
282
283 igt_subtest("hang-S3")
284 run_test(fd, 0, SUSPEND | HANG);
285 igt_subtest("hang-S4")
286 run_test(fd, 0, HIBERNATE | HANG);
287
288 igt_fixture {
289 igt_disallow_hang(fd, hang);
290 close(fd);
291 }
292 }
293