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/external/mesa3d/src/mesa/main/
Dmacros.h265 #define ZERO_4V( DST ) (DST)[0] = (DST)[1] = (DST)[2] = (DST)[3] = 0 argument
286 #define COPY_4V( DST, SRC ) \ argument
288 (DST)[0] = (SRC)[0]; \
289 (DST)[1] = (SRC)[1]; \
290 (DST)[2] = (SRC)[2]; \
291 (DST)[3] = (SRC)[3]; \
307 #define COPY_SZ_4V(DST, SZ, SRC) \ argument
310 case 4: (DST)[3] = (SRC)[3]; /* fallthrough */ \
311 case 3: (DST)[2] = (SRC)[2]; /* fallthrough */ \
312 case 2: (DST)[1] = (SRC)[1]; /* fallthrough */ \
[all …]
/external/libvpx/libvpx/vpx_dsp/
Dintrapred.c17 #define DST(x, y) dst[(x) + (y)*stride] macro
290 DST(0, 0) = AVG2(I, J); in vpx_d207_predictor_4x4_c()
291 DST(2, 0) = DST(0, 1) = AVG2(J, K); in vpx_d207_predictor_4x4_c()
292 DST(2, 1) = DST(0, 2) = AVG2(K, L); in vpx_d207_predictor_4x4_c()
293 DST(1, 0) = AVG3(I, J, K); in vpx_d207_predictor_4x4_c()
294 DST(3, 0) = DST(1, 1) = AVG3(J, K, L); in vpx_d207_predictor_4x4_c()
295 DST(3, 1) = DST(1, 2) = AVG3(K, L, L); in vpx_d207_predictor_4x4_c()
296 DST(3, 2) = DST(2, 2) = DST(0, 3) = DST(1, 3) = DST(2, 3) = DST(3, 3) = L; in vpx_d207_predictor_4x4_c()
309 DST(0, 0) = AVG2(A, B); in vpx_d63_predictor_4x4_c()
310 DST(1, 0) = DST(0, 2) = AVG2(B, C); in vpx_d63_predictor_4x4_c()
[all …]
/external/iproute2/include/
Dbpf_util.h70 #define BPF_ALU64_REG(OP, DST, SRC) \ argument
73 .dst_reg = DST, \
78 #define BPF_ALU32_REG(OP, DST, SRC) \ argument
81 .dst_reg = DST, \
88 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
91 .dst_reg = DST, \
96 #define BPF_ALU32_IMM(OP, DST, IMM) \ argument
99 .dst_reg = DST, \
106 #define BPF_MOV64_REG(DST, SRC) \ argument
109 .dst_reg = DST, \
[all …]
/external/webp/src/dsp/
Denc.c347 #define DST(x, y) dst[(x) + (y) * BPS] macro
393 DST(0, 3) = AVG3(J, K, L); in RD4()
394 DST(0, 2) = DST(1, 3) = AVG3(I, J, K); in RD4()
395 DST(0, 1) = DST(1, 2) = DST(2, 3) = AVG3(X, I, J); in RD4()
396 DST(0, 0) = DST(1, 1) = DST(2, 2) = DST(3, 3) = AVG3(A, X, I); in RD4()
397 DST(1, 0) = DST(2, 1) = DST(3, 2) = AVG3(B, A, X); in RD4()
398 DST(2, 0) = DST(3, 1) = AVG3(C, B, A); in RD4()
399 DST(3, 0) = AVG3(D, C, B); in RD4()
411 DST(0, 0) = AVG3(A, B, C); in LD4()
412 DST(1, 0) = DST(0, 1) = AVG3(B, C, D); in LD4()
[all …]
Ddec.c170 #define DST(x, y) dst[(x) + (y) * BPS] macro
302 DST(0, 3) = AVG3(J, K, L); in RD4_C()
303 DST(1, 3) = DST(0, 2) = AVG3(I, J, K); in RD4_C()
304 DST(2, 3) = DST(1, 2) = DST(0, 1) = AVG3(X, I, J); in RD4_C()
305 DST(3, 3) = DST(2, 2) = DST(1, 1) = DST(0, 0) = AVG3(A, X, I); in RD4_C()
306 DST(3, 2) = DST(2, 1) = DST(1, 0) = AVG3(B, A, X); in RD4_C()
307 DST(3, 1) = DST(2, 0) = AVG3(C, B, A); in RD4_C()
308 DST(3, 0) = AVG3(D, C, B); in RD4_C()
320 DST(0, 0) = AVG3(A, B, C); in LD4_C()
321 DST(1, 0) = DST(0, 1) = AVG3(B, C, D); in LD4_C()
[all …]
Denc_msa.c258 #define DST(x, y) dst[(x) + (y) * BPS] macro
345 DST(0, 0) = DST(1, 2) = AVG2(X, A); in VR4()
346 DST(1, 0) = DST(2, 2) = AVG2(A, B); in VR4()
347 DST(2, 0) = DST(3, 2) = AVG2(B, C); in VR4()
348 DST(3, 0) = AVG2(C, D); in VR4()
349 DST(0, 3) = AVG3(K, J, I); in VR4()
350 DST(0, 2) = AVG3(J, I, X); in VR4()
351 DST(0, 1) = DST(1, 3) = AVG3(I, X, A); in VR4()
352 DST(1, 1) = DST(2, 3) = AVG3(X, A, B); in VR4()
353 DST(2, 1) = DST(3, 3) = AVG3(A, B, C); in VR4()
[all …]
/external/bcc/src/cc/
Dlibbpf.h127 #define BPF_ALU64_REG(OP, DST, SRC) \ argument
130 .dst_reg = DST, \
135 #define BPF_ALU32_REG(OP, DST, SRC) \ argument
138 .dst_reg = DST, \
145 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
148 .dst_reg = DST, \
153 #define BPF_ALU32_IMM(OP, DST, IMM) \ argument
156 .dst_reg = DST, \
163 #define BPF_MOV64_REG(DST, SRC) \ argument
166 .dst_reg = DST, \
[all …]
/external/bcc/src/cc/includes/
Dlibbpf.h127 #define BPF_ALU64_REG(OP, DST, SRC) \ argument
130 .dst_reg = DST, \
135 #define BPF_ALU32_REG(OP, DST, SRC) \ argument
138 .dst_reg = DST, \
145 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
148 .dst_reg = DST, \
153 #define BPF_ALU32_IMM(OP, DST, IMM) \ argument
156 .dst_reg = DST, \
163 #define BPF_MOV64_REG(DST, SRC) \ argument
166 .dst_reg = DST, \
[all …]
/external/llvm-project/libclc/generic/lib/
Dgen_convert.py190 """.format(SRC=src, DST=dst, M=mode))
199 """.format(SRC=src, DST=dst, N=size, H=half_size, M=mode))
206 }}""".format(SRC=src, DST=dst, M=mode))
237 {{""".format(DST=dst, SRC=src, N=size))
244 bool_prefix = "as_{DST}{N}(convert_{BOOL}{N}".format(DST=dst, BOOL=bool_type[dst], N=size);
262 return y;""".format(SRC=src, DST=dst, N=size,
287 print(" return convert_{DST}{N}(x);".format(DST=dst, N=size))
311 """.format(DST=dst, SRC=src, N=size, M=mode))
343 {{""".format(SRC=src, DST=dst, N=size, M=mode, S=sat))
353 print(" return convert_{DST}{N}{S}(x);".format(DST=dst, N=size, S=sat))
[all …]
/external/ltp/include/lapi/
Dbpf.h444 #define BPF_ALU64_REG(OP, DST, SRC) \ argument
447 .dst_reg = DST, \
452 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
455 .dst_reg = DST, \
460 #define BPF_MOV64_REG(DST, SRC) \ argument
463 .dst_reg = DST, \
468 #define BPF_LD_IMM64(DST, IMM) \ argument
469 BPF_LD_IMM64_RAW(DST, 0, IMM)
471 #define BPF_LD_IMM64_RAW(DST, SRC, IMM) \ argument
474 .dst_reg = DST, \
[all …]
/external/skia/tools/skqp/
Drun_apk.sh17 DST="$2"
19 printf '\n\nAPK = "%s"\nDST = "%s"\n\n' "$APK" "$DST"
33 adb shell am instrument $SKQP_ARGS -w org.skia.skqp 2>&1 | tee "$DST"/stdout
35 adb logcat -d TestRunner org.skia.skqp skia DEBUG '*:S' > "$DST"/logcat
37 ODIR="$(sed -n "$SED_CMD" "$DST"/logcat | head -1)"
39 if adb shell "test -d '$ODIR'"; then adb pull "$ODIR" "$DST"; fi
Ddocker_run_apk.sh19 DST="$(mktemp -d "${TMPDIR:-/tmp}/skqp_emulated_test.XXXXXXXXXX")"
27 docker build -t android-skqp ./android-skqp/ > "$DST"/docker-build || exit 2
34 --volume="$DST":/DST \
37 android-skqp > "$DST"/docker-run || exit 3
43 "${SKQP}/../../bin/sysopen" "$DST"/skqp_report_*/report.html
/external/llvm-project/llvm/test/CodeGen/X86/
Dmempcpy.ll5 ; (2) its return value is DST+N i.e. the dst pointer adjusted by the copy size.
7 ; adjust the dst pointer, DST+N is explicitly computed and stored to a global
8 ; variable G before the mempcpy call. This instance of DST+N causes the repeat
9 ; DST+N done in the context of the return value of mempcpy to be redundant, and
11 ; (2) to be expressed as verifying that the MOV to store DST+N to G and
12 ; the MOV to copy DST+N to %rax use the same source register.
23 define i8* @RET_MEMPCPY(i8* %DST, i8* %SRC, i64 %N) {
24 %add.ptr = getelementptr inbounds i8, i8* %DST, i64 %N
26 %call = tail call i8* @mempcpy(i8* %DST, i8* %SRC, i64 %N)
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dmemccpy.ll13 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i64*
15 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 8
24 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i64*
26 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 8
35 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(5) [[DST:…
44 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(11) [[DST…
53 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(7) [[DST:…
62 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(6) [[DST:…
71 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(5) [[DST:…
80 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(11) [[DST…
[all …]
Dsprintf-1.ll25 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* nonnull align 1 dereferenceable(13) [[DST…
35 ; CHECK-NEXT: store i8 0, i8* [[DST:%.*]], align 1
45 ; CHECK-NEXT: store i8 0, i8* [[DST:%.*]], align 1
57 ; CHECK-NEXT: store i8 104, i8* [[DST:%.*]], align 1
58 ; CHECK-NEXT: [[NUL:%.*]] = getelementptr i8, i8* [[DST]], i32 1
71 ; CHECK-NEXT: [[STRCPY:%.*]] = call i8* @strcpy(i8* nonnull dereferenceable(1) [[DST:%.*]], i8* …
83 ; CHECK-IPRINTF-NEXT: [[TMP1:%.*]] = call i32 (i8*, i8*, ...) @siprintf(i8* [[DST:%.*]], i8* get…
87 …%.*]] = call i32 (i8*, i8*, ...) @sprintf(i8* nonnull dereferenceable(1) [[DST:%.*]], i8* nonnull …
99 ; CHECK-IPRINTF-NEXT: [[STPCPY:%.*]] = call i8* @stpcpy(i8* [[DST:%.*]], i8* [[STR:%.*]])
101 ; CHECK-IPRINTF-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[DST]] to i32
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dpr30451.ll13 ; CHECK: lbarx [[DST:[0-9]+]],
14 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
29 ; CHECK: lharx [[DST:[0-9]+]],
30 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
46 ; CHECK: lbarx [[DST:[0-9]+]],
47 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
62 ; CHECK: lharx [[DST:[0-9]+]],
63 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
/external/mesa3d/src/mesa/swrast/
Ds_chan.h80 #define COPY_CHAN4(DST, SRC) COPY_4UBV(DST, SRC) argument
92 #define COPY_CHAN4(DST, SRC) COPY_4V(DST, SRC) argument
104 #define COPY_CHAN4(DST, SRC) COPY_4V(DST, SRC) argument
/external/llvm-project/llvm/test/Transforms/MemCpyOpt/
Dnontemporal.ll12 ; CHECK-NEXT: store <4 x float> zeroinitializer, <4 x float>* [[DST:%.*]], align 16, !nontempora…
13 ; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 1
15 ; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 2
17 ; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 3
19 ; CHECK-NEXT: [[PTR4:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 4
21 ; CHECK-NEXT: [[PTR5:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 5
23 ; CHECK-NEXT: [[PTR6:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 6
25 ; CHECK-NEXT: [[PTR7:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 7
51 ; CHECK-NEXT: store <4 x float> zeroinitializer, <4 x float>* [[DST:%.*]], align 16, !nontempora…
52 ; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 1
Dmemset-memcpy-redundant-memset.ll12 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 [[SRC_SIZE]]
14 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC:%.*]], i64 [[SRC_SIZE]…
28 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 [[SRC_SIZE]]
30 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC:%.*]], i64 [[SRC_SIZE]…
44 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[DST:%.*]], i128 [[TMP1]]
46 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[DST]], i8* [[SRC:%.*]], i32 [[SRC_SIZE]…
60 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[DST:%.*]], i128 [[SRC_SIZE]]
62 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i128(i8* [[DST]], i8* [[SRC:%.*]], i128 [[SRC_SIZ…
76 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 [[TMP1]]
78 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[DST]], i8* [[SRC:%.*]], i32 [[SRC_SIZE]…
[all …]
Dfca2memcpy.ll12 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
24 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
36 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
51 ; CHECK-NEXT: store [[S]] [[TMP1]], %S* [[DST:%.*]], align 8
63 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
78 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
81 ; CHECK-NEXT: store [[S]] [[TMP1]], %S* [[DST]], align 8
95 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
96 ; CHECK-NEXT: [[DST2:%.*]] = getelementptr [[S:%.*]], %S* [[DST]], i64 1
113 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
[all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dvect_copyable_in_binops.ll8 ; CHECK-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 1
10 ; CHECK-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 2
12 ; CHECK-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 3
16 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[DST]] to <4 x i32>*
47 ; CHECK-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 1
48 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[DST]], align 4
52 ; CHECK-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 2
57 ; CHECK-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 3
91 ; CHECK-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 1
92 ; CHECK-NEXT: store i32 [[SUB]], i32* [[DST]], align 4
[all …]
/external/llvm-project/clang/test/CodeGenObjC/
Dnontrivial-c-struct-within-struct-name.m25 // CHECK: define linkonce_odr hidden void @__destructor_8_S_S_s0(i8** %[[DST:.*]])
27 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
32 // CHECK: define linkonce_odr hidden void @__destructor_8_S_s0(i8** %[[DST:.*]])
34 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
41 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dlower-mem-intrinsics-threshold.ll12 ; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
16 ; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
20 ; OPT0-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
27 ; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TM…
41 ; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4…
45 ; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4…
52 ; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
64 ; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TM…
78 ; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 8…
85 ; OPT4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
[all …]
/external/mesa3d/src/util/
Du_math.h762 #define COPY_4V( DST, SRC ) \ argument
764 (DST)[0] = (SRC)[0]; \
765 (DST)[1] = (SRC)[1]; \
766 (DST)[2] = (SRC)[2]; \
767 (DST)[3] = (SRC)[3]; \
773 #define COPY_4FV( DST, SRC ) COPY_4V(DST, SRC) argument
778 #define ASSIGN_4V( DST, V0, V1, V2, V3 ) \ argument
780 (DST)[0] = (V0); \
781 (DST)[1] = (V1); \
782 (DST)[2] = (V2); \
[all …]
/external/deqp/framework/common/
DtcuInterval.hpp229 #define TCU_SET_INTERVAL_BOUNDS(DST, VAR, SETLOW, SETHIGH) do \ argument
232 ::tcu::Interval& VAR##_dst_ = (DST); \
250 #define TCU_SET_INTERVAL(DST, VAR, BODY) \ argument
251 TCU_SET_INTERVAL_BOUNDS(DST, VAR, BODY, BODY)
258 #define TCU_INTERVAL_APPLY_MONOTONE1(DST, PARAM, ARG, VAR, BODY) do \ argument
261 ::tcu::Interval& VAR##_dst_ = (DST); \
284 #define TCU_INTERVAL_APPLY_MONOTONE2(DST, P0, A0, P1, A1, VAR, BODY) \ argument
286 DST, P0, A0, tmp2_, \
289 #define TCU_INTERVAL_APPLY_MONOTONE3(DST, P0, A0, P1, A1, P2, A2, VAR, BODY) \ argument
291 DST, P0, A0, tmp3_, \

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