Home
last modified time | relevance | path

Searched refs:arg32 (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/PowerPC/
Dppc64-zext.ll5 define i64 @fun(i32 %arg32) nounwind {
8 %o = zext i32 %arg32 to i64
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-zext.ll5 define i64 @fun(i32 %arg32) nounwind {
8 %o = zext i32 %arg32 to i64
/external/llvm-project/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll18 i32* %arg31, i32* %arg32, i32* %arg33, i32* %arg34, i32* %arg35) {
25 %d = select i1 %cond, i32* %arg33, i32* %arg32
26 %e = select i1 %cond, i32* %arg32, i32* %arg31
/external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll18 i32* %arg31, i32* %arg32, i32* %arg33, i32* %arg34, i32* %arg35) {
25 %d = select i1 %cond, i32* %arg33, i32* %arg32
26 %e = select i1 %cond, i32* %arg32, i32* %arg31
/external/pcre/dist2/
DRunTest201 arg32=
272 -32) arg32=yes;;
352 if [ "$arg8$arg16$arg32" = "" ] ; then
380 if [ "$arg32" = yes ] ; then
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dmemop-folding-int-arith.ll401 define void @sdiv_lhs(i32 %arg32, i64 %arg64) {
403 sdiv i32 %li32, %arg32
436 ; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %1 = sdiv i32 %li32, %arg32
457 define void @sdiv_rhs(i32 %arg32, i64 %arg64) {
459 sdiv i32 %arg32, %li32
484 ; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %1 = sdiv i32 %arg32, %li32
499 define void @udiv_lhs(i32 %arg32, i64 %arg64) {
501 udiv i32 %li32, %arg32
528 ; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %1 = udiv i32 %li32, %arg32
545 define void @udiv_rhs(i32 %arg32, i64 %arg64) {
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dschedule-kernel-arg-loads.ll29 i64 %arg32, i64 %arg33, i64 %arg34, i64 %arg35, i64 %arg36, i64 %arg37, i64 %arg38, i64 %arg39,
Dcallee-special-input-vgprs.ll539 ; frame[0] = byval arg32
563 …2 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 {
602 %private = load volatile i32, i32 addrspace(5)* %arg32
Dllvm.amdgcn.interp.ll188 …loat %arg27, float %arg28, float %arg29, float %arg30, i32 %arg31, float %arg32, float %arg33) #0 {
/external/llvm/test/CodeGen/AMDGPU/
Dschedule-kernel-arg-loads.ll34 i64 %arg32, i64 %arg33, i64 %arg34, i64 %arg35, i64 %arg36, i64 %arg37, i64 %arg38, i64 %arg39,
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtpu-variable-runtime-reformatting.mlir141 [%newvar, %arg4] as %arg32 : !tf_res_f32)
144 // %arg32 is not a pass-through.
146 "tf.TPUExecuteAndUpdateVariables"(%arg30, %arg31, %arg32, %compile#1)
/external/llvm-project/polly/test/ScopInfo/
Dmultidim_fortran_srem.ll33 …le]* noalias %arg30, [0 x double]* noalias %arg31, [0 x double]* noalias %arg32, [0 x double]* noa…
/external/llvm-project/clang/include/clang/Basic/
Darm_mve.td1243 multiclass ScalarSaturatingShiftImm<Type arg32, Type arg64> {
1244 def "": ScalarShift<arg32, (args imm_1to32:$sh),
1258 multiclass ScalarSaturatingShiftReg<Type arg32, Type arg64> {
1259 def "": ScalarShift<arg32, (args s32:$sh),
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
Dops.mlir747 …2>, %arg29: tensor<?xf32>, %arg30: tensor<?xf32>, %arg31: tensor<?xf32>, %arg32: tensor<?xf32>, %a…
748 … %arg23, %arg24, %arg25, %arg26, %arg27, %arg28, %arg29, %arg30, %arg31, %arg32, %arg33, %arg34, %…
749 … %arg23, %arg24, %arg25, %arg26, %arg27, %arg28, %arg29, %arg30, %arg31, %arg32, %arg33, %arg34, %…