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Searched refs:ADD3 (Results 1 – 25 of 53) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/Reassociate/
D	mixed-fast-nonfast-fp.ll	`10 ; CHECK-NEXT: [[ADD3:%.]] = fadd fast float [[REASS_MUL]], [[MUL3]] 11 ; CHECK-NEXT: ret float [[ADD3]] 31 ; CHECK-NEXT: [[ADD3:%.]] = fadd fast float [[ADD1]], [[ADD2]] 32 ; CHECK-NEXT: ret float [[ADD3]]`
/external/llvm-project/llvm/test/Transforms/InstCombine/
D	nsw.ll	`50 ; CHECK-NEXT: [[ADD3:%.]] = add nsw i32 [[X:%.]], 5 51 ; CHECK-NEXT: ret i32 [[ADD3]] 60 ; CHECK-NEXT: [[ADD3:%.]] = add i8 [[X:%.]], -126 61 ; CHECK-NEXT: ret i8 [[ADD3]] 70 ; CHECK-NEXT: [[ADD3:%.]] = add i8 [[X:%.]], 3 71 ; CHECK-NEXT: ret i8 [[ADD3]]`
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
D	legalize-add-v512.mir	52 ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]] 53 … G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>) 99 ; AVX1: [[ADD3:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV3]], [[UV7]] 100 … G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD3]](<8 x s16>) 146 ; AVX1: [[ADD3:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV3]], [[UV7]] 147 … G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD3]](<4 x s32>) 189 ; AVX1: [[ADD3:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV3]], [[UV7]] 190 … G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD3]](<2 x s64>) 244 ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]] 246 …; AVX1: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD2]](<16 x s8>), [[ADD3]](…
/external/llvm-project/llvm/test/Transforms/JumpThreading/
D	select-unfold-freeze.ll	`63 ; CHECK-NEXT: [[ADD3:%.]] = add nsw i32 [[J:%.]], 2 82 … = phi i32 [ [[J]], [[DOTEXIT_THREAD]] ], [ [[ADD3]], [[DOTEXIT]] ], [ [[ADD3]], [[ENTRY:%.]] ], … 115 ; CHECK-NEXT: [[ADD3:%.]] = add nsw i32 [[J:%.]], 2 136 …= phi i32 [ [[J]], [[DOTEXIT_THREAD]] ], [ [[ADD3]], [[DOTEXIT]] ], [ [[ADD3]], [[COND_FALSE_I]] ]… 172 ; CHECK-NEXT: [[ADD3:%.]] = add nsw i32 [[J:%.*]], 2`
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
D	crash_reordering_undefs.ll	`13 ; CHECK-NEXT: [[ADD3:%.]] = add i32 [[ADD1]], [[ADD2]] 16 ; CHECK-NEXT: [[ADD5:%.]] = add i32 [[ADD3]], [[ADD4]]`
D	remark_not_all_parts.ll	`20 ; CHECK-NEXT: [[ADD3:%.]] = add nsw i32 [[TMP4]], [[TMP2]] 22 ; CHECK-NEXT: store i32 [[ADD3]], i32 [[ARRAYIDX6]], align 16 23 ; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD3]], [[A_088]]`
D	intrinsic.ll	`209 ; CHECK-NEXT: [[ADD3:%.]] = add i32 [[I4]], [[I5]] 210 ; CHECK-NEXT: [[CALL3:%.]] = tail call i32 @llvm.ctlz.i32(i32 [[ADD3]], i1 true) #3 336 ; CHECK-NEXT: [[ADD3:%.]] = add i32 [[I4]], [[I5]] 337 ; CHECK-NEXT: [[CALL3:%.]] = tail call i32 @llvm.cttz.i32(i32 [[ADD3]], i1 true) #3 462 ; CHECK-NEXT: [[ADD3:%.]] = fadd float [[I4]], [[I5]] 463 ; CHECK-NEXT: [[CALL3:%.]] = tail call float @llvm.powi.f32(float [[ADD3]], i32 [[P]]) #3`
D	crash_cmpop.ll	`23 ; SSE-NEXT: [[ADD3:%.]] = fadd float [[S1_055]], [[TMP0]] 25 ; SSE-NEXT: [[ADD4:%.]] = fadd float [[MUL]], [[ADD3]]`
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/
D	ult-sub-to-eq.ll	`27 ; CHECK-NEXT: [[ADD3:%.]] = fadd float [[TMP2]], [[MUL]] 28 ; CHECK-NEXT: store float [[ADD3]], float [[ARRAYIDX2]], align 4`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	legalize-uadde.mir	`52 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ZEXT1]] 53 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD2]](s32), [[ADD3]](s32) 56 ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[ADD3]](s32), [[UV7]]`
D	legalize-mul.mir	150 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[UMULH1]] 151 ; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL3]](s32), [[ADD3]](s32) 175 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[UMULH1]] 176 ; GFX8: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL3]](s32), [[ADD3]](s32) 200 ; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[UMULH1]] 201 ; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL3]](s32), [[ADD3]](s32) 587 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[UMULH1]] 588 ; GFX6: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]] 613 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[UMULH1]] 614 ; GFX8: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]] [all …]
D	legalize-sdiv.mir	37 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[C3]] 38 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[ADD3]], [[UMULH1]] 73 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[C3]] 74 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[ADD3]], [[UMULH1]] 109 ; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[C3]] 110 ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[ADD3]], [[UMULH1]] 159 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[C3]] 160 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[ADD3]], [[UMULH1]] 227 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH1]], [[C3]] 228 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[ADD3]], [[UMULH1]] [all …]
D	legalize-bitcast.mir	555 ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[COPY4]] 559 ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD3]](s16) 594 ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC6]], [[TRUNC7]] 605 ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ADD3]](s16) 665 ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[COPY4]] 681 ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD3]](s16) 724 ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC6]], [[TRUNC7]] 750 ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ADD3]](s16) 829 ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC7]] 836 ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ADD3]](s16) [all …]
D	legalize-udiv.mir	137 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]] 138 ; GFX6: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[UV1]], [[ADD3]] 186 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]] 187 ; GFX8: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[UV1]], [[ADD3]] 235 ; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]] 236 ; GFX9: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[UV1]], [[ADD3]] 307 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] 310 ; GFX6: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] 460 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] 463 ; GFX8: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] [all …]
D	legalize-phi.mir	282 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]] 293 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32) 450 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV7]] 451 …R:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32) 502 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV11]] 507 …<8 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s3… 558 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV19]] 571 …16 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s3… 621 ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV35]] 650 …32 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s3… [all …]
D	legalize-srem.mir	155 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[ASHR2]] 157 ; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[ADD3]], [[ASHR2]] 216 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[ASHR2]] 218 ; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[ADD3]], [[ASHR2]] 277 ; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[ASHR2]] 279 ; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[ADD3]], [[ASHR2]] 376 ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] 379 ; GFX6: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] 543 ; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] 546 ; GFX8: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] [all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU/
D	reduction.ll	23 ; VI-NEXT: [[ADD3:%.]] = fadd fast half [[ELT3]], [[ADD2]] 24 ; VI-NEXT: ret half [[ADD3]] 63 ; VI-NEXT: [[ADD3:%.]] = fadd fast half [[ELT3]], [[ADD2]] 64 ; VI-NEXT: [[ADD4:%.]] = fadd fast half [[ELT4]], [[ADD3]] 125 ; VI-NEXT: [[ADD3:%.]] = fadd fast half [[ELT3]], [[ADD2]] 126 ; VI-NEXT: [[ADD4:%.]] = fadd fast half [[ELT4]], [[ADD3]] 187 ; GCN-NEXT: [[ADD3:%.]] = fsub fast half [[ELT3]], [[ADD2]] 188 ; GCN-NEXT: ret half [[ADD3]] 221 ; VI-NEXT: [[ADD3:%.*]] = add i16 [[ELT3]], [[ADD2]] 222 ; VI-NEXT: ret i16 [[ADD3]] [all …]
/external/llvm-project/llvm/test/Transforms/LoopVectorize/ARM/
D	tail-folding-not-allowed.ll	93 ; CHECK-NEXT: [[I_09:%.]] = phi i32 [ 0, [[ENTRY:%.]] ], [ [[ADD3:%.]], [[FOR_BODY]] ] 101 ; CHECK-NEXT: [[ADD3]] = add nuw nsw i32 [[I_09]], 1 102 ; CHECK-NEXT: [[EXITCOND:%.]] = icmp eq i32 [[ADD3]], 431 233 ; CHECK-NEXT: [[I_09:%.]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[ADD3:%.]], [[FOR… 241 ; CHECK-NEXT: [[ADD3]] = add nuw nsw i32 [[I_09]], 1 242 ; CHECK-NEXT: [[ADD_IV:%.]] = trunc i32 [[ADD3]] to i16 321 ; CHECK-NEXT: [[I_09:%.]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[ADD3:%.]], [[FOR… 330 ; CHECK-NEXT: [[ADD3]] = add nuw nsw i32 [[I_09]], 1 331 ; CHECK-NEXT: [[EXITCOND:%.]] = icmp eq i32 [[ADD3]], 431 389 ; CHECK-NEXT: [[I_09:%.]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[ADD3:%.]], [[LOO… [all …]
D	tail-folding-prefer-flag.ll	`55 ; PREDFLAG: %[[ADD3:.]] = add i32 %index, 8 59 …LM3:active.lane.mask.]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %[[ADD3]], i32 %N)`
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
D	cttz.mir	`143 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]] 144 ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]] 149 ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)`
D	ctpop.mir	`82 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]] 83 ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]]`
D	mul.mir	`300 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]] 301 ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]] 304 ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]] 396 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]] 397 ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]] 400 ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]`
/external/pdfium/third_party/libopenjpeg20/
D	dwt.c	622 #define ADD3(x,y,z) ADD(ADD(x,y),z) macro 683 s0n_0 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 684 s0n_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 698 s0n_0 = SUB(s1n_0, SAR(ADD3(d1c_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 699 s0n_1 = SUB(s1n_1, SAR(ADD3(d1c_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 718 tmp_len_minus_1 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 726 tmp_len_minus_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2() 781 SAR(ADD3(LOADU(in_even + 0), s1_0, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2() 787 SAR(ADD3(LOADU(in_even + VREG_INT_COUNT), s1_1, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2() 798 SAR(ADD3(s1_0, s2_0, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2() [all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	reduction.ll	101 ; GFX9-NEXT: v_pk_add_f16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}} 102 ; GFX9-NEXT: v_add_f16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src… 127 ; GFX9-NEXT: v_pk_add_u16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}} 128 ; GFX9-NEXT: v_add_u16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src… 157 ; GFX9-NEXT: v_pk_add_f16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}} 158 ; GFX9-NEXT: v_add_f16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/ARM/
D	sroa.ll	`44 ; CHECK-NEXT: [[ADD3:%.]] = fadd double [[TMP1]], [[TMP3]] 48 ; CHECK-NEXT: store double [[ADD3]], double [[IM_I_I]], align 4`

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