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Searched refs:ADDVI_H (Results 1 – 15 of 15) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dadd_vec_builtin.mir179 ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18
180 ; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
/external/webp/src/dsp/
Dmsa_macro.h26 #define ADDVI_H(a, b) __msa_addvi_h((v8i16)a, b) macro
37 #define ADDVI_H(a, b) (a + b) macro
1133 out0 = (RTYPE)ADDVI_H(in0, in1); \
1134 out1 = (RTYPE)ADDVI_H(in2, in3); \
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp399 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST); in legalizeIntrinsic()
DMipsMSAInstrInfo.td2764 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp537 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST); in legalizeIntrinsic()
DMipsMSAInstrInfo.td2784 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc78 2281722002U, // ADDVI_H
1867 0U, // ADDVI_H
5043 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,...
DMipsGenDisassemblerTables.inc1550 /* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmWriter.inc1924 268456451U, // ADDVI_H
4678 4U, // ADDVI_H
7225 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
DMipsGenMCCodeEmitter.inc696 UINT64_C(2015363078), // ADDVI_H
4072 case Mips::ADDVI_H:
10158 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 683
DMipsGenDAGISel.inc15978 /* 29476*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_H), 0,
15981 … // Dst: (ADDVI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
15984 /* 29488*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_H), 0,
15987 … // Dst: (ADDVI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
DMipsGenInstrInfo.inc698 ADDVI_H = 683,
5544 …, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #683 = ADDVI_H
DMipsGenDisassemblerTables.inc3877 /* 5313 */ MCD::OPC_Decode, 171, 5, 239, 1, // Opcode: ADDVI_H
DMipsGenAsmMatcher.inc5546 …{ 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,…
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2738 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;