| /external/llvm-project/clang/test/CodeGenOpenCLCXX/ |
| D | address-space-deduction.cl | 6 #define ADR(x) x
9 #define ADR(x) &x
16 int PTR glob_p = ADR(glob);
32 int PTR loc_p = ADR(loc);
34 const __private int PTR loc_p_const = ADR(loc);
38 static int PTR loc_st_p = ADR(loc_st);
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | select-gv-cmodel-tiny.mir | 33 ; CHECK: [[ADR:%[0-9]+]]:gpr64 = ADR @foo1
34 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]]
35 ; CHECK: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2
|
| /external/llvm-project/llvm/test/CodeGen/MIR/AArch64/ |
| D | mir-canon-constant-pool-hash.mir | 17 ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
18 ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | jump-table-compress.mir | 80 …; First destination is (2^20 - 4) after reference. Just reachable by ADR so can use compressed tab…
94 ; First destination is 2^20 before reference. Just within reach of ADR.
104 ; First destination is 2^20 before reference. Just within reach of ADR.
|
| D | aarch64-interleaved-ld-combine.ll | 73 ; AS-DAG: add [[ADR:x[0-9]+]], x0, [[AND]]
74 …{ v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}}
135 ; AS-DAG: add [[ADR:x[0-9]+]], [[ADD]], [[AND]]
136 …{ v[[V0:[0-9]+]].4s, v[[V1:[0-9]+]].4s, v[[V2:[0-9]+]].4s, v[[V3:[0-9]+]].4s }, {{\[}}[[ADR]]{{\]}}
|
| /external/llvm-project/llvm/test/Transforms/IndVarSimplify/ |
| D | no-iv-rewrite.ll | 22 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDVARS_IV]]
23 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
76 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDVARS_IV]]
77 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
131 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[PTRIV]], i64 [[OFS]]
132 ; CHECK-NEXT: store i32 3, i32* [[ADR]], align 4
173 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr [[STRUCTI:%.*]], %structI* [[P]], i32 0, i32 0
174 ; CHECK-NEXT: store i32 3, i32* [[ADR]], align 4
216 ; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[BASE:%.*]], i64 [[INDVARS_IV]]
217 ; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
[all …]
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | macho-adrp-missing-reloc.s | 3 ; CHECK: error: ADR/ADRP relocations must be GOT relative
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
|
| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 108 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
117 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 108 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
117 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | jump-table-islands-split.ll | 8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | jump-table-islands-split.ll | 8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
|
| /external/arm-trusted-firmware/fdts/ |
| D | fvp-defs.dtsi | 39 #define ADR(n, c, p) \ macro
80 ADR(n, c, p) \
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 125 [ADR, ADRP,
|
| D | AArch64MacroFusion.cpp | 219 case AArch64::ADR: in isAddressLdStPair()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 125 [ADR, ADRP,
|
| D | AArch64MacroFusion.cpp | 219 case AArch64::ADR: in isAddressLdStPair()
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 908 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
909 if (!ADR) in validateRootSet()
914 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
916 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 892 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
893 if (!ADR) in validateRootSet()
898 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
900 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 967 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(V.BaseInst)); in findRoots() local
968 if (!ADR) in findRoots()
982 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(V.Roots[0]), ADR); in findRoots()
984 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) { in findRoots()
|
| /external/vixl/src/aarch64/ |
| D | instructions-aarch64.cc | 911 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in GetImmPCOffsetTarget()
951 if ((Mask(PCRelAddressingMask) == ADR)) { in SetPCRelImmTarget()
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 55 # ADR
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 55 # ADR
|
| /external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ds-5_trace_dump/ |
| D | a15_rs.txt | 76 S:0x8000056C E28F1E16 ADR r1,{pc}+0x168 ; 0x800006d4
214 S:0x80000882 A614 ADR r6,{pc}+0x52 ; 0x800008d4
412 S:0x8000056C E28F1E16 ADR r1,{pc}+0x168 ; 0x800006d4
550 S:0x80000882 A614 ADR r6,{pc}+0x52 ; 0x800008d4
764 S:0x8000056C E28F1E16 ADR r1,{pc}+0x168 ; 0x800006d4
902 S:0x80000882 A614 ADR r6,{pc}+0x52 ; 0x800008d4
1116 S:0x8000056C E28F1E16 ADR r1,{pc}+0x168 ; 0x800006d4
1254 S:0x80000882 A614 ADR r6,{pc}+0x52 ; 0x800008d4
1468 S:0x8000056C E28F1E16 ADR r1,{pc}+0x168 ; 0x800006d4
1606 S:0x80000882 A614 ADR r6,{pc}+0x52 ; 0x800008d4
[all …]
|
| /external/tremolo/Tremolo/ |
| D | dpen.s | 69 ADR r14,dpen_read_return
466 ADR r6,.Lcrc_lookup
|