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Searched refs:ARG5 (Results 1 – 23 of 23) sorted by relevance

/external/llvm-project/mlir/test/Conversion/StandardToSPIRV/
Dlegalization.mlir20 …: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG…
23 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[ARG5]] : index
35 …ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: f32
44 // CHECK: store [[ARG5]], [[ARG0]]{{\[}}[[INDEX1]], [[INDEX2]]{{\]}}
52 …: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG…
55 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[ARG5]] : index
85 …: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: vector<4xf32>
94 …// CHECK: vector.transfer_write [[ARG5]], [[ARG0]]{{\[}}[[INDEX1]], [[INDEX2]]{{\]}} {masked = [fa…
/external/llvm-project/mlir/test/Dialect/Affine/
Dloop-tiling-parametric.mlir21 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO2]](){{.*}}[[ARG2]]
24 … affine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI2]]{{.*}}[…
50 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO2]](){{.*}}[[ARG2]]{{.*}} step 2
53 … affine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI2]]{{.*}}[…
118 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9+]]] = 8 to [[UBO1]]{{.*}}[[ARG2]]{{.*}} step 4
121 …NEXT: affine.for %[[K:.*]] = [[LBI0]]([[ARG5]]){{.*}}[[ARG2]]{{.*}} to min [[UBI2]]([[A…
146 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO1]](){{.*}}[[ARG2]]{{.*}}
149 … affine.for %[[K:.*]] = [[LBI]]{{.*}}[[ARG5]]{{.*}}[[ARG2]]{{.*}} to min [[UBI1]]{{.*}}[…
240 // CHECK-NEXT: affine.for [[ARG5:%arg[0-9]+]] = 0 to [[UBO1]]({{.*}}){{.*}}[[ARG1]]
242 …ECK-NEXT: affine.for {{.*}} = [[LBI0]]([[ARG5]]){{.*}}[[ARG1]]{{.*}} to min [[UBI1]]({{.*}},…
[all …]
/external/llvm-project/mlir/test/Dialect/Linalg/
Dtile-simple-conv.mlir30 // CHECK: scf.for %[[ARG5:.*]] = %[[C0]] to %[[T4]] step %[[C4]]
36 // CHECK: %[[T10:.*]] = affine.min #[[MAP2]](%[[ARG5]])[%[[T1]], %[[T9]]]
38 // CHECK: %[[SV1:.*]] = subview %[[ARG1]][%[[ARG3]], %[[ARG4]], %[[ARG5]], 0]
45 // CHECK: %[[T18:.*]] = affine.min #[[MAP5]](%[[ARG5]])[%[[T17]]]
47 // CHECK: %[[SV2:.*]] = subview %[[ARG2]][%[[ARG3]], %[[ARG4]], %[[ARG5]], 0]
Dtile-parallel-reduce.mlir19 // CHECK: scf.for %[[ARG5:.*]] =
21 // CHECK: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG5]]]
22 // CHECK: %[[SV2:.*]] = subview %{{.*}}[%[[ARG5]], %[[ARG4]]]
81 // CHECK: scf.for %[[ARG5:.*]] =
83 // CHECK: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]], %[[ARG5]]]
84 // CHECK: %[[SV2:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG5]]]
Dreshape_fusion.mlir230 // CHECK-SAME: %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
238 // CHECK: %[[T9:.+]] = index_cast %[[ARG5]]
273 // CHECK-SAME: %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
275 // CHECK: %[[T3:.+]] = affine.apply #[[MAP]](%[[ARG3]], %[[ARG4]], %[[ARG5]])
335 // CHECK-SAME: %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
339 // CHECK-DAG: %[[T4:.+]] = affine.apply #[[MAP6]](%[[ARG4]], %[[ARG5]], %[[ARG6]])
387 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]+]]: i32)
390 // CHECK: %[[T2:.+]] = addi %[[ARG5]], %[[T1]] : i32
Dtile-and-distribute.mlir82 // CHECK: scf.for %[[ARG5:.*]] =
83 // CHECK: %[[SV1:.*]] = subview %[[ARG0]][%[[ARG3]], %[[ARG5]]]
84 // CHECK: %[[SV2:.*]] = subview %[[ARG1]][%[[ARG5]], %[[ARG4]]]
/external/llvm-project/mlir/test/Conversion/OpenMPToLLVM/
Dconvert-to-llvmir.mlir33 …%[[ARG2:.*]]: !llvm.i64, %[[ARG3:.*]]: !llvm.i64, %[[ARG4:.*]]: !llvm.i64, %[[ARG5:.*]]: !llvm.i64)
38 // CHECK: (%[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[ARG4]], %[[ARG5]])
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtpu_parallel_execute_sink_resource_write.mlir98 …+]]: tensor<i64>, [[ARG3:%.+]]: tensor<f32>, [[ARG4:%.+]]: tensor<f64>, [[ARG5:%.+]]: tensor<!tf.r…
102 // CHECK-NEXT: "tf.AssignVariableOp"([[ARG5]], [[ARG1]])
119 …]]: tensor<i64>, [[ARG3:%.+]]: tensor<bf16>, [[ARG4:%.+]]: tensor<f32>, [[ARG5:%.+]]: tensor<f64>,…
129 // CHECK-NEXT: tf_device.return [[ARG3]], [[ARG5]] : tensor<bf16>, tensor<f64>
/external/llvm-project/mlir/test/Dialect/SCF/
Dparallel-loop-tiling.mlir18 …: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG…
22 // CHECK: [[V1:%.*]] = muli [[ARG5]], [[C1]] : index
27 …arallel ([[V7:%.*]], [[V8:%.*]]) = ([[C0]], [[C0]]) to ([[V5]], [[V6]]) step ([[ARG5]], [[ARG6]]) {
/external/strace/tests-mx32/
Dfutex.c92 ARG5 = 1 << 2, enumerator
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests/
Dfutex.c92 ARG5 = 1 << 2, enumerator
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests-m32/
Dfutex.c92 ARG5 = 1 << 2, enumerator
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/llvm/test/CodeGen/XCore/
Dscavenging.ll57 ; CHECK: [[ARG5:.LCPI[0-9_]+]]:
78 ; CHECK: ldw r4, cp{{\[}}[[ARG5]]{{\]}}
/external/llvm-project/llvm/test/CodeGen/XCore/
Dscavenging.ll57 ; CHECK: [[ARG5:.LCPI[0-9_]+]]:
78 ; CHECK: ldw r4, cp{{\[}}[[ARG5]]{{\]}}
/external/llvm-project/mlir/test/Conversion/GPUToSPIRV/
Dload-store.mlir36 …// CHECK-SAME: %[[ARG5:.*]]: i32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 5), StorageBu…
/external/llvm-project/mlir/test/Conversion/StandardToLLVM/
Dconvert-dynamic-memref-ops.mlir200 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
221 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
255 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
276 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
Dconvert-to-llvmir.mlir1080 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
1091 // CHECK32-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i32
1155 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
1166 // CHECK32-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i32
Dconvert-static-memref-ops.mlir295 // CHECK-SAME: %[[ARG5:[a-zA-Z0-9]*]]: !llvm.i64
/external/tensorflow/tensorflow/compiler/mlir/tools/kernel_gen/tests/
Dtf_abi_knowledge.mlir29 …// ABI-SAME: %[[ARG2:.*]]: i64, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: !llvm.ptr<f32>…
31 …lvm.ptr<f32>, %[[ARG2:.*]]: i64, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: !llvm.ptr<f32…
53 // SHAPE-NEXT: llvm.insertvalue %[[ARG5]]
/external/llvm-project/llvm/test/Transforms/DeadStoreElimination/MSSA/
Dsimple.ll257 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0
259 ; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]])
/external/llvm-project/mlir/test/Conversion/SCFToStandard/
Dconvert-to-cfg.mlir475 // CHECK: ^[[AFTER]](%[[ARG4:.*]]: i64, %[[ARG5:.*]]: f64):
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/hlo_to_lhlo_with_xla/
Dhlo_text_to_lhlo_no_opt.hlotxt29 // CHECK: ^bb0(%[[ARG5:.*]]: tensor<i32>, %[[ARG6:.*]]: tensor<i32>):
/external/llvm-project/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/
Dsimple.ll484 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0
486 ; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]])