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Searched refs:ARG6 (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/mlir/test/Conversion/StandardToSPIRV/
Dlegalization.mlir20 …G2:%.*]]: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG6:%.*]]: index
25 // CHECK: [[STRIDE2:%.*]] = muli [[ARG4]], [[ARG6]] : index
52 …: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG6:%.*]]: index, [[ARG…
57 // CHECK: [[STRIDE2:%.*]] = muli [[ARG4]], [[ARG6]] : index
/external/llvm-project/mlir/test/Conversion/OpenMPToLLVM/
Dconvert-to-llvmir.mlir40 // CHECK: ^{{.*}}(%[[ARG6:.*]]: !llvm.i64, %[[ARG7:.*]]: !llvm.i64):
42 // CHECK: "test.payload"(%[[ARG6]], %[[ARG7]]) : (!llvm.i64, !llvm.i64) -> ()
/external/strace/tests-mx32/
Dfutex.c93 ARG6 = 1 << 3, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests/
Dfutex.c93 ARG6 = 1 << 3, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests-m32/
Dfutex.c93 ARG6 = 1 << 3, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtpu_parallel_execute_sink_resource_write.mlir98 …or<f32>, [[ARG4:%.+]]: tensor<f64>, [[ARG5:%.+]]: tensor<!tf.resource>, [[ARG6:%.+]]: tensor<!tf.r…
103 // CHECK-NEXT: "tf.AssignVariableOp"([[ARG6]], [[ARG3]])
119 …]]: tensor<bf16>, [[ARG4:%.+]]: tensor<f32>, [[ARG5:%.+]]: tensor<f64>, [[ARG6:%.+]]: tensor<!tf.r…
123 // CHECK-NEXT: "tf.AssignVariableOp"([[ARG6]], [[ARG1]])
/external/llvm-project/mlir/test/Dialect/SCF/
Dparallel-loop-tiling.mlir18 …: index, [[ARG3:%.*]]: index, [[ARG4:%.*]]: index, [[ARG5:%.*]]: index, [[ARG6:%.*]]: index, [[ARG…
23 // CHECK: [[V2:%.*]] = muli [[ARG6]], [[C4]] : index
27 …arallel ([[V7:%.*]], [[V8:%.*]]) = ([[C0]], [[C0]]) to ([[V5]], [[V6]]) step ([[ARG5]], [[ARG6]]) {
/external/llvm-project/mlir/test/Dialect/Linalg/
Dreshape_fusion.mlir231 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32)
233 // CHECK: %[[T4:.+]] = muli %[[ARG6]], %[[ARG7]]
274 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32)
276 // CHECK: %[[T4:.+]] = muli %[[ARG6]], %[[ARG7]]
336 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]+]]: index, %[[ARG7:[a-zA-Z0-9]+]]: index,
339 // CHECK-DAG: %[[T4:.+]] = affine.apply #[[MAP6]](%[[ARG4]], %[[ARG5]], %[[ARG6]])
/external/llvm-project/mlir/test/Conversion/GPUToSPIRV/
Dload-store.mlir37 …// CHECK-SAME: %[[ARG6:.*]]: i32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 6), StorageBu…
/external/llvm-project/mlir/test/Conversion/StandardToLLVM/
Dconvert-dynamic-memref-ops.mlir201 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
222 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
256 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
277 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
Dconvert-to-llvmir.mlir1081 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
1092 // CHECK32-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i32
1156 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
1167 // CHECK32-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i32
Dconvert-static-memref-ops.mlir296 // CHECK-SAME: %[[ARG6:[a-zA-Z0-9]*]]: !llvm.i64
/external/tensorflow/tensorflow/compiler/mlir/tools/kernel_gen/tests/
Dtf_abi_knowledge.mlir29 …4, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: !llvm.ptr<f32>, %[[ARG6:.*]]: !llvm.ptr<f32…
31 …4, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: !llvm.ptr<f32>, %[[ARG6:.*]]: !llvm.ptr<f32…
52 // ABI-NEXT: llvm.insertvalue %[[ARG6]]
55 // CHECK-NEXT: llvm.insertvalue %[[ARG6]]
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/hlo_to_lhlo_with_xla/
Dhlo_text_to_lhlo_no_opt.hlotxt29 // CHECK: ^bb0(%[[ARG5:.*]]: tensor<i32>, %[[ARG6:.*]]: tensor<i32>):
30 // CHECK: "mhlo.return"(%[[ARG6]])