| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 623 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
1421 COMPARE_BOTH(Adc(r0, r1, 0xbadbeef), in TEST()
1526 COMPARE_BOTH(Adc(r0, r1, -2), "sbc r0, r1, #1\n"); in TEST()
1543 COMPARE_BOTH(Adc(r0, r1, 0xabcd), in TEST()
1547 COMPARE_BOTH(Adc(r0, r1, -0xabcd), in TEST()
1551 COMPARE_BOTH(Adc(r0, r1, 0x1234abcd), in TEST()
1556 COMPARE_BOTH(Adc(r0, r1, -0x1234abcd), in TEST()
1584 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
2599 COMPARE_A32(Adc(pc, r0, 1), "adc pc, r0, #1\n"); in TEST()
2600 COMPARE_A32(Adc(r0, pc, 1), "adc r0, pc, #1\n"); in TEST()
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| D | test-assembler-aarch32.cc | 243 __ Adc(r4, r2, r3); in TEST() local
244 __ Adc(r5, r0, Operand(r1, LSL, 30)); in TEST() local
245 __ Adc(r6, r0, Operand(r2, LSR, 16)); in TEST() local
246 __ Adc(r7, r2, Operand(r3, ASR, 4)); in TEST() local
247 __ Adc(r8, r2, Operand(r3, ROR, 8)); in TEST() local
248 __ Adc(r9, r2, Operand(r3, RRX)); in TEST() local
271 __ Adc(r5, r2, r3); in TEST() local
272 __ Adc(r6, r0, Operand(r1, LSL, 30)); in TEST() local
273 __ Adc(r7, r0, Operand(r2, LSR, 16)); in TEST() local
274 __ Adc(r8, r2, Operand(r3, ASR, 4)); in TEST() local
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 M(Adc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 116 M(Adc) \
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 5231 __ Adc(x5, x2, Operand(x3)); in TEST() local
5232 __ Adc(x6, x0, Operand(x1, LSL, 60)); in TEST() local
5234 __ Adc(x8, x2, Operand(x3, ASR, 4)); in TEST() local
5235 __ Adc(x9, x2, Operand(x3, ROR, 8)); in TEST() local
5237 __ Adc(w10, w2, Operand(w3)); in TEST() local
5238 __ Adc(w11, w0, Operand(w1, LSL, 30)); in TEST() local
5240 __ Adc(w13, w2, Operand(w3, ASR, 4)); in TEST() local
5241 __ Adc(w14, w2, Operand(w3, ROR, 8)); in TEST() local
5246 __ Adc(x18, x2, Operand(x3)); in TEST() local
5247 __ Adc(x19, x0, Operand(x1, LSL, 60)); in TEST() local
[all …]
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| D | test-disasm-aarch64.cc | 2785 COMPARE_MACRO(Adc(x0, x1, 0x4242), in TEST()
2788 COMPARE_MACRO(Adc(x0, x0, 0x4242), in TEST()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 381 Adc, enumerator
1003 using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
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| D | IceInstX86Base.h | 76 Adc, enumerator
1389 class InstX86Adc : public InstX86BaseBinopGPR<InstX86Base::Adc> {
1397 : InstX86BaseBinopGPR<InstX86Base::Adc>(Func, Dest, Source) {} in InstX86Adc()
3216 using Adc = typename InstImpl<TraitsType>::InstX86Adc; member
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| D | IceTargetLoweringX86Base.h | 518 Context.insert<typename Traits::Insts::Adc>(Dest, Src0); in _adc()
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| D | IceInstARM32.cpp | 3486 template class InstARM32ThreeAddrGPR<InstARM32::Adc>;
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 992 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { in Adc() function
1006 void Adc(Register rd, Register rn, const Operand& operand) { in Adc() function
1007 Adc(al, rd, rn, operand); in Adc()
1009 void Adc(FlagsUpdate flags, in Adc() function
1016 Adc(cond, rd, rn, operand); in Adc()
1028 Adc(cond, rd, rn, operand); in Adc()
1033 void Adc(FlagsUpdate flags, in Adc() function
1037 Adc(flags, al, rd, rn, operand); in Adc()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1809 void MacroAssembler::Adc(const Register& rd, in Adc() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 762 void Adc(const Register& rd, const Register& rn, const Operand& operand);
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