| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 167 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
181 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
184 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
194 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
198 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
213 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 431 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 81 uint16_t AddSubOpc; // Expanded add / sub opcode member
115 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4798 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4806 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
360 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
363 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 383 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 58 uint16_t AddSubOpc; // Expanded add / sub opcode member
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4150 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4158 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 486 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 85 uint16_t AddSubOpc; // Expanded add / sub opcode member
119 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4834 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4842 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9798 unsigned ShiftAmt, AddSubOpc; in performMulCombine() local
9812 AddSubOpc = ISD::ADD; in performMulCombine()
9815 AddSubOpc = ISD::SUB; in performMulCombine()
9825 AddSubOpc = ISD::SUB; in performMulCombine()
9829 AddSubOpc = ISD::ADD; in performMulCombine()
9842 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 11660 unsigned ShiftAmt, AddSubOpc; in performMulCombine() local
11674 AddSubOpc = ISD::ADD; in performMulCombine()
11677 AddSubOpc = ISD::SUB; in performMulCombine()
11687 AddSubOpc = ISD::SUB; in performMulCombine()
11691 AddSubOpc = ISD::ADD; in performMulCombine()
11704 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
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