/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 230 let AltOrders = [(add LR, GPR), (trunc GPR, 8), 242 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8), 254 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 267 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)]; 275 let AltOrders = [(add LR, GPRwithZRnosp), (trunc GPRwithZRnosp, 8)]; 300 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8), 328 let AltOrders = [(and tcGPR, tGPR)]; 335 let AltOrders = [(and tGPROdd, tGPR)]; 344 let AltOrders = [(and tGPREven, tGPR)]; 371 let AltOrders = [(add (decimate SPR, 2), SPR), [all …]
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 230 let AltOrders = [(add LR, GPR), (trunc GPR, 8), 242 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8), 254 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 267 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)]; 275 let AltOrders = [(add LR, GPRwithZRnosp), (trunc GPRwithZRnosp, 8)]; 300 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8), 339 let AltOrders = [(and tcGPR, tGPR)]; 346 let AltOrders = [(and tGPROdd, tGPR)]; 355 let AltOrders = [(and tGPREven, tGPR)]; 382 let AltOrders = [(add (decimate SPR, 2), SPR), [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 200 let AltOrders = [(add LR, GPR), (trunc GPR, 8)]; 210 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 220 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 238 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; 256 let AltOrders = [(and tcGPR, tGPR)]; 273 let AltOrders = [(add (decimate SPR, 2), SPR), 295 let AltOrders = [(rotl DPR, 16), 316 let AltOrders = [(rotl QPR, 8)]; 342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))]; 377 let AltOrders = [(rotl QQPR, 8)]; [all …]
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 290 let AltOrders = [(add (sub GPRC, R2), R2)]; 301 let AltOrders = [(add (sub G8RC, X2), X2)]; 313 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)]; 322 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)]; 385 let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT, 396 let AltOrders = [(sub CRRC, CR2, CR3, CR4)];
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/external/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 238 let AltOrders = [(add (sub GPRC, R2), R2)]; 250 let AltOrders = [(add (sub G8RC, X2), X2)]; 263 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)]; 273 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 261 let AltOrders = [(add (sub GPRC, R2), R2)]; 272 let AltOrders = [(add (sub G8RC, X2), X2)]; 284 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)]; 293 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
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/external/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 131 let AltOrders = [(rotl GPR32common, 8)]; 136 let AltOrders = [(rotl GPR64common, 8)]; 141 let AltOrders = [(rotl GPR32, 8)]; 145 let AltOrders = [(rotl GPR64, 8)]; 151 let AltOrders = [(rotl GPR32sp, 8)]; 155 let AltOrders = [(rotl GPR64sp, 8)];
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 142 let AltOrders = [(rotl GPR32common, 8)]; 147 let AltOrders = [(rotl GPR64common, 8)]; 152 let AltOrders = [(rotl GPR32, 8)]; 156 let AltOrders = [(rotl GPR64, 8)]; 162 let AltOrders = [(rotl GPR32sp, 8)]; 166 let AltOrders = [(rotl GPR64sp, 8)];
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 139 let AltOrders = [(rotl GPR32common, 8)]; 144 let AltOrders = [(rotl GPR64common, 8)]; 149 let AltOrders = [(rotl GPR32, 8)]; 153 let AltOrders = [(rotl GPR64, 8)]; 159 let AltOrders = [(rotl GPR32sp, 8)]; 163 let AltOrders = [(rotl GPR64sp, 8)];
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/external/llvm/utils/TableGen/ |
D | CodeGenRegisters.cpp | 677 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local 678 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass() 691 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass() 692 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
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/external/llvm-project/llvm/utils/TableGen/ |
D | CodeGenRegisters.cpp | 759 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local 760 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass() 775 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass() 776 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 392 let AltOrders = [(decimate FGR32, 2)]; 413 let AltOrders = [(decimate FGR64, 2)];
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 392 let AltOrders = [(decimate FGR32, 2)]; 413 let AltOrders = [(decimate FGR64, 2)];
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 331 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 383 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 402 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 468 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 392 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 458 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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/external/llvm/include/llvm/Target/ |
D | Target.td | 195 // AltOrders - List of alternative allocation orders. The default order is 199 list<dag> AltOrders = []; 208 // MemberList, 1 to select the first AltOrders entry and so on.
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/external/llvm-project/llvm/include/llvm/Target/ |
D | Target.td | 257 // AltOrders - List of alternative allocation orders. The default order is 261 list<dag> AltOrders = []; 270 // MemberList, 1 to select the first AltOrders entry and so on.
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
D | Target.td | 256 // AltOrders - List of alternative allocation orders. The default order is 260 list<dag> AltOrders = []; 269 // MemberList, 1 to select the first AltOrders entry and so on.
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