| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 1596 COMPARE_T32(Asr(r2, r2, Operand(r2, ROR, r2)), in TEST()
1600 COMPARE_T32(Asr(r2, r2, Operand(r2, ROR, r2)), in TEST()
3259 COMPARE_T32(Asr(eq, r0, r1, 16), in TEST()
3263 COMPARE_T32(Asr(eq, r0, r1, 32), in TEST()
3267 COMPARE_T32(Asr(eq, r0, r1, 0), in TEST()
3273 COMPARE_T32(Asr(eq, r7, r7, r3), in TEST()
3277 COMPARE_T32(Asr(eq, r8, r8, r3), in TEST()
4025 CHECK_T32_16(Asr(DontCare, r0, r1, 32), "asrs r0, r1, #32\n"); in TEST()
4027 CHECK_T32_16_IT_BLOCK(Asr(DontCare, eq, r0, r1, 32), in TEST()
4031 CHECK_T32_16(Asr(DontCare, r0, r0, r1), "asrs r0, r1\n"); in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 142 M(Asr) \
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 142 M(Asr) \
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| D | test-assembler-aarch32.cc | 785 __ Asr(r5, r1, 16); in TEST() local
813 __ Asr(r5, r1, r9); in TEST() local
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 1003 void Asr(Register rd, Register rm, const Operand& shift_imm,
1006 void Asr(Register rd, Register rm, Register rs, Condition cond = AL);
1033 Asr(reg, reg, Operand(kSmiTagSize), cond);
1037 Asr(dst, src, Operand(kSmiTagSize), cond);
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| D | assembler_arm.cc | 2475 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
2500 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
2521 Asr(rd, rm, Operand(31), cond); in SignFill()
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 196 __ Asr(PickR(size), PickR(size), 4); in GenerateTrivialSequence() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 384 Asr, enumerator
1006 using InstARM32Asr = InstARM32ThreeAddrGPR<InstARM32::Asr>;
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| D | IceInstARM32.cpp | 3489 template class InstARM32ThreeAddrGPR<InstARM32::Asr>;
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 6280 __ Asr(x16, x0, x1); in TEST() local
6281 __ Asr(x17, x0, x2); in TEST() local
6282 __ Asr(x18, x0, x3); in TEST() local
6283 __ Asr(x19, x0, x4); in TEST() local
6284 __ Asr(x20, x0, x5); in TEST() local
6285 __ Asr(x21, x0, x6); in TEST() local
6287 __ Asr(w22, w0, w1); in TEST() local
6288 __ Asr(w23, w0, w2); in TEST() local
6289 __ Asr(w24, w0, w3); in TEST() local
6290 __ Asr(w25, w0, w4); in TEST() local
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| D | test-assembler-sve-aarch64.cc | 11970 masm->Asr(ztmp, ztmp, kQRegSizeInBytesLog2 - dst.GetLaneSizeInBytesLog2()); in IntSegmentPatternHelper()
12754 __ Asr(zd_asr, zn, shift); in BitwiseShiftImmHelper() local
12843 macro = &MacroAssembler::Asr; in BitwiseShiftWideElementsHelper()
13051 __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnB()); in TEST_SVE() local
13057 __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnH()); in TEST_SVE() local
13063 __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnS()); in TEST_SVE() local
13068 __ Asr(z13.VnD(), p0.Merging(), z31.VnD(), z1.VnD()); in TEST_SVE() local
13126 __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnD()); in TEST_SVE() local
13131 __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnD()); in TEST_SVE() local
13136 __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnD()); in TEST_SVE() local
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| D | test-disasm-sve-aarch64.cc | 294 COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()), in TEST()
296 COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()), in TEST()
298 COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()), in TEST()
352 COMPARE_MACRO(Asr(z8.VnH(), p7.Merging(), z29.VnH(), 3), in TEST()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1075 void Asr(const Register& rd, const Register& rn, unsigned shift) { in Asr() function
1082 void Asr(const Register& rd, const Register& rn, const Register& rm) { in Asr() function
3534 void Asr(const ZRegister& zd, in Asr() function
3542 void Asr(const ZRegister& zd,
3546 void Asr(const ZRegister& zd, const ZRegister& zn, int shift) { in Asr() function
3551 void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Asr() function
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| D | macro-assembler-sve-aarch64.cc | 565 void MacroAssembler::Asr(const ZRegister& zd, in Asr() function in vixl::aarch64::MacroAssembler
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1232 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { in Asr() function
1249 void Asr(Register rd, Register rm, const Operand& operand) { in Asr() function
1250 Asr(al, rd, rm, operand); in Asr()
1252 void Asr(FlagsUpdate flags, in Asr() function
1259 Asr(cond, rd, rm, operand); in Asr()
1273 Asr(cond, rd, rm, operand); in Asr()
1278 void Asr(FlagsUpdate flags, in Asr() function
1282 Asr(flags, al, rd, rm, operand); in Asr()
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