| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | vec-trunc-to-i1.ll | 6 define void @pr32275(<4 x i8> %B15) {
23 %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
|
| /external/llvm-project/llvm/test/Transforms/SCCP/ |
| D | latticeval-invalidate.ll | 28 %B15 = sub i64 %B8, %B23
30 %G29 = getelementptr i32**, i32*** undef, i64 %B15
|
| /external/harfbuzz_ng/test/shaping/data/text-rendering-tests/tests/ |
| D | SHBALI-1.tests | 2 ….ttf:--font-size=1000 --ned --remove-default-ignorables --font-funcs=ft:U+1B15,U+1B44,U+1B16,U+1B0…
16 …ze=1000 --ned --remove-default-ignorables --font-funcs=ft:U+1B13,U+1B44,U+1B15,U+1B3E:[gid66|gid23…
21 …ze=1000 --ned --remove-default-ignorables --font-funcs=ft:U+1B13,U+1B44,U+1B15,U+1B3E:[gid66|gid23…
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s1935737938.ll | 39 %B15 = frem float 0.000000e+00, 0.000000e+00
41 %Cmp17 = fcmp one float 0xBD946F9840000000, %B15
60 %Sl30 = select i1 true, float 0x45B13EA500000000, float %B15
|
| D | llvm-stress-s3926023935.ll | 41 %B15 = sdiv i64 334618, -1
74 %Cmp39 = icmp eq i64 498254, %B15
|
| D | llvm-stress-s1704963983.ll | 41 %B15 = udiv <1 x i16> %B, zeroinitializer
|
| D | llvm-stress-s997348632.ll | 38 %B15 = fdiv <4 x double> %FC, %FC
|
| D | llvm-stress-s525530439.ll | 39 %B15 = or i16 -1, %E12
|
| D | llvm-stress-s3997499501.ll | 45 %B15 = fadd double %L5, 0.000000e+00
|
| /external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s1935737938.ll | 39 %B15 = frem float 0.000000e+00, 0.000000e+00
41 %Cmp17 = fcmp one float 0xBD946F9840000000, %B15
60 %Sl30 = select i1 true, float 0x45B13EA500000000, float %B15
|
| D | llvm-stress-s3926023935.ll | 41 %B15 = sdiv i64 334618, -1
74 %Cmp39 = icmp eq i64 498254, %B15
|
| D | llvm-stress-s997348632.ll | 38 %B15 = fdiv <4 x double> %FC, %FC
|
| D | llvm-stress-s525530439.ll | 39 %B15 = or i16 -1, %E12
|
| D | llvm-stress-s1704963983.ll | 41 %B15 = udiv <1 x i16> %B, zeroinitializer
|
| D | llvm-stress-s3861334421.ll | 41 %B15 = srem i64 %Sl10, 380809
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 127 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
167 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 231 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;
265 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
300 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
335 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
370 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 126 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
166 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 126 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
166 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | and-or-icmps.ll | 219 ; CHECK-NEXT: [[B15:%.*]] = xor i1 [[C7]], [[C10]]
220 ; CHECK-NEXT: [[B19:%.*]] = xor i1 [[C11]], [[B15]]
251 %B15 = add i1 %C7, %C10
252 %B19 = add i1 %C11, %B15
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 267 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;
301 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
336 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
371 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
406 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 264 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;
298 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
333 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
368 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
403 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
|
| /external/crosvm/devices/src/usb/xhci/ |
| D | xhci_abi.rs | 353 reserved1: B15,
370 reserved4: B15,
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | fmaddsub-combine.ll | 327 %B15 = extractelement <16 x float> %B, i32 15
328 %add15 = fadd float %A15, %B15
596 %B15 = extractelement <16 x float> %B, i32 15
597 %add15 = fsub float %A15, %B15
|
| /external/protobuf/python/google/protobuf/internal/ |
| D | more_messages.proto | 119 message B15 {} message
|