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Searched refs:B21 (Results 1 – 25 of 72) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp57 static constexpr IValueT B21 = 1 << 21; variable
1125 constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6; in emitMoveSS()
1261 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode; in emitSIMDCvtqq()
1392 const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 | in bkpt()
1440 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 | in blx()
1452 B21 | (0xfff << 8) | B4 | in bx()
1474 B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4; in clz()
1524 B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 | in dmb()
1851 B24 | B21 | B15 | B14 | B13 | B12; in nop()
2083 constexpr IValueT MlaOpcode = B21; in mla()
[all …]
/external/llvm-project/llvm/test/Transforms/ADCE/
D2016-09-06.ll20 br i1 %I10, label %B11, label %B21
44 br label %B21
46 B21:
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc315 B24 | B22 | B21 | (0xf << 16) |
377 EmitMulOp(cond, B21, ra, rd, rn, rm);
386 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
412 EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm); in umlal()
458 EmitDivOp(cond, B21 , rd, rn, rm);
574 B21 | B20 | (0xff << 12) | B4 | 0xf; in clrex()
583 B25 | B24 | B21 | (0xf << 12);
673 (i*B21) |
881 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
886 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
[all …]
Dassembler_arm.h64 B21 = 1 << 21,
597 return (AL << kConditionShift) | B24 | B21 |
/external/llvm/test/CodeGen/PowerPC/
Dbv-widen-undef.ll16 %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1>
21 %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dbv-widen-undef.ll16 %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1>
21 %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0
/external/llvm-project/llvm/test/CodeGen/Generic/
Ddag-combine-ossfuzz-crash.ll22 %B21 = urem i1 %C11, true
47 store i1 %B21, i1* undef
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h133 case AArch64::D21: return AArch64::B21; in getBRegFromDReg()
173 case AArch64::B21: return AArch64::D21; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td237 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;
271 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
306 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
341 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
376 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
/external/llvm-project/llvm/test/MC/COFF/
Dcv-loc-unreachable.s39 # CODEVIEW-NEXT: 0B21 code 0xA (+0x1) line 2 (+1)
Dcv-loc-unreachable-2.s28 # CODEVIEW-NEXT: 0B21 code 0xA (+0x1) line 2 (+1)
/external/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h132 case AArch64::D21: return AArch64::B21; in getBRegFromDReg()
172 case AArch64::B21: return AArch64::D21; in getDRegFromBReg()
/external/llvm-project/llvm/test/CodeGen/X86/
Dknown-bits.ll56 %B21 = udiv i8 %Sl9, -93
61 %I40 = insertelement <4 x i8> zeroinitializer, i8 %B21, i32 1
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h132 case AArch64::D21: return AArch64::B21; in getBRegFromDReg()
172 case AArch64::B21: return AArch64::D21; in getDRegFromBReg()
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dand-or-icmps.ll241 %B21 = sdiv i16 %L7, %L4
242 %B7 = sub i16 0, %B21
247 %C5 = icmp sle i16 %B21, %L
248 %C11 = icmp ule i16 %B21, %L
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td273 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;
307 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
342 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
377 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
412 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td270 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;
304 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
339 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
374 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
409 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
/external/protobuf/python/google/protobuf/internal/
Dmore_messages.proto125 message B21 {} message
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini92 B21=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini92 B21=0x00000000 key
/external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/
Dunroll-n-jam-smlad.ll179 %B21 = load i16, i16* %arrayidx4.us.i.3356.i, align 2
180 %conv.us.i.3357.i = sext i16 %B21 to i32
/external/icu/icu4c/source/data/unidata/norm2/
Dnfc.txt749 0B5C>0B21 0B3C
2140 2F8EF>6B21
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Darith-sub-usubo.ll337 ; CHECK-NEXT: [[B21:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
369 ; CHECK-NEXT: [[C21:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A21]], i16 [[B21…
696 ; CHECK-NEXT: [[B21:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
760 ; CHECK-NEXT: [[C21:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A21]], i8 [[B21]])
Darith-add-uaddo.ll337 ; CHECK-NEXT: [[B21:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
369 ; CHECK-NEXT: [[C21:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A21]], i16 [[B21…
696 ; CHECK-NEXT: [[B21:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
760 ; CHECK-NEXT: [[C21:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A21]], i8 [[B21]])
Darith-sub-ssubo.ll337 ; CHECK-NEXT: [[B21:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
369 ; CHECK-NEXT: [[C21:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A21]], i16 [[B21…
696 ; CHECK-NEXT: [[B21:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
760 ; CHECK-NEXT: [[C21:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A21]], i8 [[B21]])

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