| /external/llvm-project/clang/test/CodeGenCXX/ |
| D | dllexport-no-dllexport-inlines.cpp | 69 class B22{}; class
80 TemplateExportedClass<B22> b22;
105 extern template class __declspec(dllimport) TemplateNoAttributeClass<B22>;
108 TemplateNoAttributeClass<B22> b22; in TemplateNoAttributeClassUser()
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| /external/llvm-project/llvm/test/CodeGen/Generic/ |
| D | dag-combine-ossfuzz-crash.ll | 25 %B22 = udiv i66 %B9, %B1
37 %B16 = urem i66 %B22, %L6
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| /external/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s1935737938.ll | 50 %B22 = urem i32 135673, %3
61 %Cmp31 = icmp eq i32 %B22, %B22
99 %I56 = insertelement <4 x i32> %I42, i32 %B22, i32 2
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| D | llvm-stress-s1704963983.ll | 50 %B22 = urem <8 x i64> %Shuff7, %I21
112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
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| D | llvm-stress-s3997499501.ll | 60 %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
69 …%Shuff26 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %B22, <4 x i32> <i32 undef, i32 unde…
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| D | llvm-stress-s997348632.ll | 50 %B22 = xor <8 x i32> %I14, %I14
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| D | llvm-stress-s3926023935.ll | 50 %B22 = fadd double 0.000000e+00, %BC
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| /external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
| D | llvm-stress-s1935737938.ll | 50 %B22 = urem i32 135673, %3
61 %Cmp31 = icmp eq i32 %B22, %B22
99 %I56 = insertelement <4 x i32> %I42, i32 %B22, i32 2
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| D | llvm-stress-s1704963983.ll | 50 %B22 = urem <8 x i64> %Shuff7, %I21
112 %I65 = insertelement <8 x i64> %B22, i64 %L47, i32 7
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| D | llvm-stress-s3997499501.ll | 60 %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
69 …%Shuff26 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %B22, <4 x i32> <i32 undef, i32 unde…
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| D | llvm-stress-s3926023935.ll | 50 %B22 = fadd double 0.000000e+00, %BC
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| D | llvm-stress-s997348632.ll | 50 %B22 = xor <8 x i32> %I14, %I14
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| /external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/ |
| D | unroll-n-jam-smlad.ll | 182 %B22 = load i16, i16* %arrayidx5.us.i.3358.i, align 2
183 %conv6.us.i.3359.i = sext i16 %B22 to i32
192 %B22.dup = load i16, i16* %arrayidx5.us.i.1.3.i, align 2
193 %conv6.us.i.1.3.i = sext i16 %B22.dup to i32
201 %B22.dup.i = load i16, i16* %arrayidx5.us.i.2.3.i, align 2
202 %conv6.us.i.2.3.i = sext i16 %B22.dup.i to i32
210 %B22.dup.i.i = load i16, i16* %arrayidx5.us.i.3.3.i, align 2
211 %conv6.us.i.3.3.i = sext i16 %B22.dup.i.i to i32
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| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | udiv-simplify.ll | 80 %B22 = add i177 %B9, %B13
82 %C9 = icmp ult i177 %Y, %B22
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 37 return (encoding_ & ~kOffset12Mask) | B22 |
315 B24 | B22 | B21 | (0xf << 16) |
335 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
386 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
397 EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm); in smull()
423 EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm); in umaal()
573 int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 | in clrex()
633 B26 | B22 | (static_cast<int32_t>(rt2) * B16) | in vmovsrr()
654 B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) | in vmovrrs()
693 B27 | B26 | B22 |
[all …]
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| /external/crosvm/devices/src/usb/xhci/ |
| D | xhci_abi.rs | 360 reserved1: B22,
399 reserved0: B22,
415 reserved0: B22,
432 reserved1: B22,
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 134 case AArch64::D22: return AArch64::B22; in getBRegFromDReg()
174 case AArch64::B22: return AArch64::D22; in getDRegFromBReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 238 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
272 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
307 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
342 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
377 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
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| /external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 133 case AArch64::D22: return AArch64::B22; in getBRegFromDReg()
173 case AArch64::B22: return AArch64::D22; in getDRegFromBReg()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | known-bits.ll | 57 %B22 = udiv i8 %Sl9, 93
62 %I41 = insertelement <4 x i8> zeroinitializer, i8 %B22, i32 1
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 133 case AArch64::D22: return AArch64::B22; in getBRegFromDReg()
173 case AArch64::B22: return AArch64::D22; in getDRegFromBReg()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 58 static constexpr IValueT B22 = 1 << 22; variable
444 Value = Value | B22 | ((Imm8 & 0xf0) << 4) | (Imm8 & 0x0f); in encodeImmRegOffsetEnc3()
1474 B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4; in clz()
1523 (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 | in dmb()
1778 IValueT Opcode = B25 | B24 | (IsMovW ? 0 : B22); in emitMovwt()
2101 constexpr IValueT MlsOpcode = B22 | B21; in mls()
2144 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit()
2322 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; in uxt()
3106 IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 | in vmovdrr()
3158 IValueT Encoding = B27 | B26 | B22 | B20 | B11 | B9 | B8 | B4 | in vmovrrd()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 274 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
308 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
343 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
378 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
413 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 271 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
305 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
340 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
375 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
410 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
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| /external/protobuf/python/google/protobuf/internal/ |
| D | more_messages.proto | 126 message B22 {} message
|