| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 267 BFM, // Insert a range of bits into a 32-bit word. enumerator
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| D | AMDGPUInstrInfo.td | 202 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 3478 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
3481 (BFM $a, $b)
3486 (BFM $a, (MOV 0))
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_fmt_def.inc | 483 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
494 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 431 BFM, // Insert a range of bits into a 32-bit word. enumerator
|
| D | AMDGPUInstrInfo.td | 268 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 2333 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
2336 (BFM $a, $b)
2341 (BFM $a, (MOV (i32 0)))
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 420 BFM, // Insert a range of bits into a 32-bit word. enumerator
|
| D | AMDGPUInstrInfo.td | 284 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 1957 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
1960 (BFM $a, $b)
1965 (BFM $a, (MOV (i32 0)))
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert.ll | 200 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert.ll | 241 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 169 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedA57.td | 159 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
|
| D | AArch64ISelDAGToDAG.cpp | 1734 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1737 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 171 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedTSV110.td | 405 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(S|U)?BFM(W|X)ri$")>;
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| D | AArch64SchedThunderX3T110.td | 813 def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "^BFM")>;
814 def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "(S|U)?BFM.*")>;
|
| D | AArch64SchedThunderX2T99.td | 553 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>;
554 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>;
|
| D | AArch64SchedA57.td | 161 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 170 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
|
| D | AArch64SchedThunderX2T99.td | 553 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>;
554 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>;
|
| D | AArch64SchedA57.td | 160 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
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| D | AArch64InstructionSelector.cpp | 2861 MachineInstr &BFM = in selectMergeValues() local
2870 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues()
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| D | AArch64ISelDAGToDAG.cpp | 1917 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1920 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
|