Searched refs:BRW_OPCODE_F16TO32 (Results 1 – 13 of 13) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_shader.cpp | 180 if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32) in brw_instruction_name()
964 case BRW_OPCODE_F16TO32: in can_do_saturate()
1012 case BRW_OPCODE_F16TO32: in can_do_cmod()
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| D | brw_eu_defines.h | 221 BRW_OPCODE_F16TO32, /**< Gen7 only */ enumerator
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| D | brw_eu.cpp | 629 { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GEN7 | GEN75 },
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| D | brw_ir_performance.cpp | 306 case BRW_OPCODE_F16TO32: in instruction_desc()
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| D | brw_fs_nir.cpp | 1647 bld.emit(BRW_OPCODE_F16TO32, tmp32, tmp16); in nir_emit_alu()
1682 inst = bld.emit(BRW_OPCODE_F16TO32, result, in nir_emit_alu()
1690 inst = bld.emit(BRW_OPCODE_F16TO32, result, in nir_emit_alu()
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| D | brw_vec4_generator.cpp | 1622 case BRW_OPCODE_F16TO32: in generate_code()
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| D | brw_fs_generator.cpp | 2100 case BRW_OPCODE_F16TO32: in generate_code()
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| D | brw_eu_emit.c | 1304 return brw_alu1(p, BRW_OPCODE_F16TO32, dst, src); in brw_F16TO32()
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| D | brw_fs.cpp | 6199 if (inst->opcode == BRW_OPCODE_F16TO32) in is_mixed_float_with_fp32_dst()
6527 case BRW_OPCODE_F16TO32: in get_lowered_simd_width()
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| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 97 "f16to32" { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; }
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| D | brw_defines.h | 651 BRW_OPCODE_F16TO32 = 20, enumerator
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| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 80 f16to32 { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; }
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| D | i965_gram.y | 113 case BRW_OPCODE_F16TO32: in i965_asm_unary_instruction()
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