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Searched refs:BRW_VERTICAL_STRIDE_4 (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dtest_eu_validate.cpp319 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
358 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
630 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
634 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
663 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
670 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
785 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
794 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
837 { BRW_VERTICAL_STRIDE_4, true }, in TEST_P()
983 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4); in TEST_P()
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Dbrw_eu_validate.c950 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in general_restrictions_on_region_parameters()
955 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in general_restrictions_on_region_parameters()
965 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in general_restrictions_on_region_parameters()
970 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in general_restrictions_on_region_parameters()
1139 ERROR_IF(brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in special_restrictions_for_mixed_float_mode()
1143 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_4, in special_restrictions_for_mixed_float_mode()
Dbrw_disasm.c1025 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4; in vstride_from_align1_3src_vstride()
1052 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4; in vstride_from_align1_3src_hstride()
1074 case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4; in implied_width()
1158 _vert_stride = BRW_VERTICAL_STRIDE_4; in src0_3src()
1231 _vert_stride = BRW_VERTICAL_STRIDE_4; in src1_3src()
1318 _vert_stride = BRW_VERTICAL_STRIDE_4; in src2_3src()
Dbrw_reg.h494 BRW_VERTICAL_STRIDE_4, in brw_vec4_reg()
863 BRW_VERTICAL_STRIDE_4, /* ? */ in brw_ip_reg()
Dbrw_eu_defines.h1024 BRW_VERTICAL_STRIDE_4 = 3, enumerator
Dbrw_eu_emit.c323 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); in brw_set_src0()
334 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); in brw_set_src0()
430 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); in brw_set_src1()
441 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); in brw_set_src1()
757 case BRW_VERTICAL_STRIDE_4: in to_3src_align1_vstride()
Dbrw_vec4_generator.cpp1918 src[0].vstride = BRW_VERTICAL_STRIDE_4; in generate_code()
2046 src[0].vstride = BRW_VERTICAL_STRIDE_4; in generate_code()
Dbrw_fs_generator.cpp1337 vstride = BRW_VERTICAL_STRIDE_4; in generate_ddx()
/external/igt-gpu-tools/assembler/
Dgen8_instruction.c224 gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_4); in gen8_set_src0()
312 gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_4); in gen8_set_src1()
Dbrw_reg.h261 BRW_VERTICAL_STRIDE_4, in brw_vec4_reg()
536 BRW_VERTICAL_STRIDE_4, /* ? */ in brw_ip_reg()
Dbrw_defines.h823 #define BRW_VERTICAL_STRIDE_4 3 macro
Dbrw_eu_emit.c342 insn->bits2.da16.src0_vert_stride = BRW_VERTICAL_STRIDE_4; in brw_set_src0()
429 insn->bits3.da16.src1_vert_stride = BRW_VERTICAL_STRIDE_4; in brw_set_src1()