Searched refs:BRW_WIDTH_2 (Results 1 – 11 of 11) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | test_eu_validate.cpp | 222 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
728 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
737 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
988 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
1060 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
1090 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
1411 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2); in TEST_P()
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| D | brw_eu_defines.h | 1041 BRW_WIDTH_2 = 1, enumerator
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| D | brw_reg.h | 512 BRW_WIDTH_2, in brw_vec2_reg()
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| D | brw_fs_generator.cpp | 179 brw_reg.width = BRW_WIDTH_2; in brw_reg_from_fs_reg()
1334 width = BRW_WIDTH_2; in generate_ddx()
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| D | brw_disasm.c | 1073 case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2; in implied_width()
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| D | brw_vec4.cpp | 2591 hw_reg->width = BRW_WIDTH_2; in apply_logical_swizzle()
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| D | brw_eu_emit.c | 1120 src0.width = BRW_WIDTH_2; in ALU1()
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| D | brw_fs.cpp | 3334 BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, in emit_repclear_shader()
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| /external/igt-gpu-tools/assembler/ |
| D | brw_reg.h | 277 BRW_WIDTH_2, in brw_vec2_reg()
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| D | gram.y | 1006 $4.width = BRW_WIDTH_2; /* execution size must be 2. */
1014 src0.reg.width = BRW_WIDTH_2;
1032 dst_null_reg.width = BRW_WIDTH_2; /* execution size of RET should be 2 */
1036 $5.reg.width = BRW_WIDTH_2;
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| D | brw_defines.h | 833 #define BRW_WIDTH_2 1 macro
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