| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 292 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
293 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
294 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 135 bool shouldClusterMemOps(const MachineOperand &BaseOp1,
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| D | AArch64InstrInfo.cpp | 2366 bool AArch64InstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1, in shouldClusterMemOps() argument
2369 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2371 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
2374 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2378 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
2415 if (BaseOp1.isFI()) { in shouldClusterMemOps()
2416 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
2421 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2350 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2352 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2362 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2363 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2364 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2369 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2392 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2632 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2634 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2636 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
2639 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2643 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
2680 if (BaseOp1.isFI()) { in shouldClusterMemOps()
2681 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
2686 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 402 const MachineOperand &BaseOp1, in memOpsHaveSameBasePtr() argument
407 if (!BaseOp1.isReg() || !BaseOp2.isReg()) in memOpsHaveSameBasePtr()
410 if (BaseOp1.isIdenticalTo(BaseOp2)) in memOpsHaveSameBasePtr()
436 bool SIInstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1, in shouldClusterMemOps() argument
439 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
442 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOp1, SecondLdSt, BaseOp2)) in shouldClusterMemOps()
2530 const MachineOperand *BaseOp0, *BaseOp1; in checkInstOffsetsDoNotOverlap() local
2534 getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
2535 if (!BaseOp0->isIdenticalTo(*BaseOp1)) in checkInstOffsetsDoNotOverlap()
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| D | SIInstrInfo.h | 189 bool shouldClusterMemOps(const MachineOperand &BaseOp1,
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1271 virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1, in shouldClusterMemOps() argument
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 694 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
696 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) && in addLoopCarriedDependences()
698 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 773 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
776 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
780 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|