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Searched refs:BaseOps (Results 1 – 25 of 26) sorted by relevance

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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInsertHardClauses.cpp109 SmallVector<const MachineOperand *, 4> BaseOps; member
150 SmallVector<const MachineOperand *, 4> BaseOps; in runOnMachineFunction() local
152 if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2, in runOnMachineFunction()
168 !SII->shouldClusterMemOps(CI.BaseOps, BaseOps, 2, 2)))) { in runOnMachineFunction()
179 CI.BaseOps = std::move(BaseOps); in runOnMachineFunction()
183 CI = ClauseInfo{Type, &MI, &MI, 1, std::move(BaseOps)}; in runOnMachineFunction()
DSIInstrInfo.cpp273 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
294 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
330 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
363 BaseOps.push_back(RSrc); in getMemOperandsWithOffsetWidth()
364 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
370 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
374 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
392 BaseOps.push_back(&LdSt.getOperand(SRsrcIdx)); in getMemOperandsWithOffsetWidth()
397 BaseOps.push_back(&LdSt.getOperand(I)); in getMemOperandsWithOffsetWidth()
399 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth()
[all …]
DSIInstrInfo.h190 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dcluster_stores.ll9 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
10 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
11 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
12 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
13 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
14 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
54 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
55 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
56 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
57 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
[all …]
/external/rust/crates/gdbstub/src/gdbstub_impl/
Dmod.rs18 target::ext::base::BaseOps,
138 BaseOps::SingleThread(_) => SINGLE_THREAD_TID, in run()
139 BaseOps::MultiThread(ops) => { in run()
382 BaseOps::SingleThread(ops) => ops.read_registers(&mut regs), in handle_base()
383 BaseOps::MultiThread(ops) => { in handle_base()
408 BaseOps::SingleThread(ops) => ops.write_registers(&regs), in handle_base()
409 BaseOps::MultiThread(ops) => ops.write_registers(&regs, self.current_mem_tid), in handle_base()
430 BaseOps::SingleThread(ops) => ops.read_addrs(addr, data), in handle_base()
431 BaseOps::MultiThread(ops) => { in handle_base()
449 BaseOps::SingleThread(ops) => ops.write_addrs(addr, cmd.val), in handle_base()
[all …]
/external/rust/crates/gdbstub/src/target/
Dmod.rs210 fn base_ops(&mut self) -> ext::base::BaseOps<Self::Arch, Self::Error>; in base_ops()
261 fn base_ops(&mut self) -> ext::base::BaseOps<Self::Arch, Self::Error> {
/external/crosvm/src/
Dgdb.rs21 use gdbstub::target::ext::base::BaseOps;
139 fn base_ops(&mut self) -> BaseOps<Self::Arch, Self::Error> { in base_ops()
140 BaseOps::SingleThread(self) in base_ops()
/external/rust/crates/gdbstub/src/target/ext/base/
Dmod.rs11 pub enum BaseOps<'a, A, E> { enum
/external/llvm-project/llvm/lib/CodeGen/
DMachineScheduler.cpp1491 SmallVector<const MachineOperand *, 4> BaseOps; member
1495 MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps, in MemOpInfo()
1497 : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset), in MemOpInfo()
1522 if (std::lexicographical_compare(BaseOps.begin(), BaseOps.end(), in operator <()
1523 RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <()
1526 if (std::lexicographical_compare(RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <()
1527 BaseOps.begin(), BaseOps.end(), Compare)) in operator <()
1627 if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength, in clusterNeighboringMemOps()
1689 SmallVector<const MachineOperand *, 4> BaseOps; in collectMemOpRecords() local
1693 if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, in collectMemOpRecords()
[all …]
DTargetInstrInfo.cpp1077 SmallVector<const MachineOperand *, 4> BaseOps; in getMemOperandWithOffset() local
1079 if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, in getMemOperandWithOffset()
1081 BaseOps.size() != 1) in getMemOperandWithOffset()
1083 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
/external/rust/crates/gdbstub/examples/armv4t/gdb/
Dmod.rs36 fn base_ops(&mut self) -> target::ext::base::BaseOps<Self::Arch, Self::Error> { in base_ops()
37 target::ext::base::BaseOps::SingleThread(self) in base_ops()
/external/rust/crates/gdbstub/examples/armv4t_multicore/
Dgdb.rs51 fn base_ops(&mut self) -> target::ext::base::BaseOps<Self::Arch, Self::Error> { in base_ops()
52 target::ext::base::BaseOps::MultiThread(self) in base_ops()
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.h72 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
DLanaiInstrInfo.cpp799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
818 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h120 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
DAArch64InstrInfo.cpp2133 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2143 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h209 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
DHexagonInstrInfo.cpp2974 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2981 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrInfo.h333 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h521 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
DPPCInstrInfo.cpp2294 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
2301 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h1276 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp3299 auto BaseOps = {Cond}; in visitSelect() local
3384 BaseOps = {}; in visitSelect()
3390 BaseOps = {}; in visitSelect()
3403 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp3129 SmallVector<SDValue, 1> BaseOps(1, Cond); in visitSelect() local
3220 BaseOps.clear(); in visitSelect()
3226 BaseOps.clear(); in visitSelect()
3242 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2751 auto BaseOps = {Cond}; in visitSelect() local
2829 BaseOps = {}; in visitSelect()
2834 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()

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