/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIInsertHardClauses.cpp | 109 SmallVector<const MachineOperand *, 4> BaseOps; member 150 SmallVector<const MachineOperand *, 4> BaseOps; in runOnMachineFunction() local 152 if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2, in runOnMachineFunction() 168 !SII->shouldClusterMemOps(CI.BaseOps, BaseOps, 2, 2)))) { in runOnMachineFunction() 179 CI.BaseOps = std::move(BaseOps); in runOnMachineFunction() 183 CI = ClauseInfo{Type, &MI, &MI, 1, std::move(BaseOps)}; in runOnMachineFunction()
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D | SIInstrInfo.cpp | 273 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 294 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth() 330 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth() 363 BaseOps.push_back(RSrc); in getMemOperandsWithOffsetWidth() 364 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth() 370 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth() 374 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth() 392 BaseOps.push_back(&LdSt.getOperand(SRsrcIdx)); in getMemOperandsWithOffsetWidth() 397 BaseOps.push_back(&LdSt.getOperand(I)); in getMemOperandsWithOffsetWidth() 399 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth() [all …]
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D | SIInstrInfo.h | 190 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | cluster_stores.ll | 9 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8 10 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8 11 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 12 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 13 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 14 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 54 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8 55 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8 56 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 57 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4 [all …]
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/external/rust/crates/gdbstub/src/gdbstub_impl/ |
D | mod.rs | 18 target::ext::base::BaseOps, 138 BaseOps::SingleThread(_) => SINGLE_THREAD_TID, in run() 139 BaseOps::MultiThread(ops) => { in run() 382 BaseOps::SingleThread(ops) => ops.read_registers(&mut regs), in handle_base() 383 BaseOps::MultiThread(ops) => { in handle_base() 408 BaseOps::SingleThread(ops) => ops.write_registers(®s), in handle_base() 409 BaseOps::MultiThread(ops) => ops.write_registers(®s, self.current_mem_tid), in handle_base() 430 BaseOps::SingleThread(ops) => ops.read_addrs(addr, data), in handle_base() 431 BaseOps::MultiThread(ops) => { in handle_base() 449 BaseOps::SingleThread(ops) => ops.write_addrs(addr, cmd.val), in handle_base() [all …]
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/external/rust/crates/gdbstub/src/target/ |
D | mod.rs | 210 fn base_ops(&mut self) -> ext::base::BaseOps<Self::Arch, Self::Error>; in base_ops() 261 fn base_ops(&mut self) -> ext::base::BaseOps<Self::Arch, Self::Error> {
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/external/crosvm/src/ |
D | gdb.rs | 21 use gdbstub::target::ext::base::BaseOps; 139 fn base_ops(&mut self) -> BaseOps<Self::Arch, Self::Error> { in base_ops() 140 BaseOps::SingleThread(self) in base_ops()
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/external/rust/crates/gdbstub/src/target/ext/base/ |
D | mod.rs | 11 pub enum BaseOps<'a, A, E> { enum
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/external/llvm-project/llvm/lib/CodeGen/ |
D | MachineScheduler.cpp | 1491 SmallVector<const MachineOperand *, 4> BaseOps; member 1495 MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps, in MemOpInfo() 1497 : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset), in MemOpInfo() 1522 if (std::lexicographical_compare(BaseOps.begin(), BaseOps.end(), in operator <() 1523 RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <() 1526 if (std::lexicographical_compare(RHS.BaseOps.begin(), RHS.BaseOps.end(), in operator <() 1527 BaseOps.begin(), BaseOps.end(), Compare)) in operator <() 1627 if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength, in clusterNeighboringMemOps() 1689 SmallVector<const MachineOperand *, 4> BaseOps; in collectMemOpRecords() local 1693 if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, in collectMemOpRecords() [all …]
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D | TargetInstrInfo.cpp | 1077 SmallVector<const MachineOperand *, 4> BaseOps; in getMemOperandWithOffset() local 1079 if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, in getMemOperandWithOffset() 1081 BaseOps.size() != 1) in getMemOperandWithOffset() 1083 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
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/external/rust/crates/gdbstub/examples/armv4t/gdb/ |
D | mod.rs | 36 fn base_ops(&mut self) -> target::ext::base::BaseOps<Self::Arch, Self::Error> { in base_ops() 37 target::ext::base::BaseOps::SingleThread(self) in base_ops()
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/external/rust/crates/gdbstub/examples/armv4t_multicore/ |
D | gdb.rs | 51 fn base_ops(&mut self) -> target::ext::base::BaseOps<Self::Arch, Self::Error> { in base_ops() 52 target::ext::base::BaseOps::MultiThread(self) in base_ops()
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/external/llvm-project/llvm/lib/Target/Lanai/ |
D | LanaiInstrInfo.h | 72 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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D | LanaiInstrInfo.cpp | 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 818 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.h | 120 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
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D | AArch64InstrInfo.cpp | 2133 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 2143 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.h | 209 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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D | HexagonInstrInfo.cpp | 2974 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 2981 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86InstrInfo.h | 333 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.h | 521 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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D | PPCInstrInfo.cpp | 2294 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 2301 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
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/external/llvm-project/llvm/include/llvm/CodeGen/ |
D | TargetInstrInfo.h | 1276 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGBuilder.cpp | 3299 auto BaseOps = {Cond}; in visitSelect() local 3384 BaseOps = {}; in visitSelect() 3390 BaseOps = {}; in visitSelect() 3403 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGBuilder.cpp | 3129 SmallVector<SDValue, 1> BaseOps(1, Cond); in visitSelect() local 3220 BaseOps.clear(); in visitSelect() 3226 BaseOps.clear(); in visitSelect() 3242 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGBuilder.cpp | 2751 auto BaseOps = {Cond}; in visitSelect() local 2829 BaseOps = {}; in visitSelect() 2834 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end()); in visitSelect()
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