| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 220 __ Bics(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence() local
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| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 997 __ Bics(r0, r1, r1); in TEST() local
1009 __ Bics(r0, r0, Operand(r1, LSL, 4)); in TEST() local
1021 __ Bics(r0, r0, Operand(r1, LSR, 4)); in TEST() local
1033 __ Bics(r0, r0, Operand(r1, ASR, 4)); in TEST() local
1045 __ Bics(r0, r0, Operand(r1, ROR, 1)); in TEST() local
1059 __ Bics(r2, r0, Operand(r1, RRX)); in TEST() local
1074 __ Bics(r2, r0, Operand(r1, RRX)); in TEST() local
1085 __ Bics(r0, r0, 0xf000); in TEST() local
1096 __ Bics(r0, r0, 0x7fffffff); in TEST() local
3286 __ Bics(r0, r0, 0); in TEST() local
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 123 M(Bics) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 123 M(Bics) \
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 778 void MacroAssembler::Bics(const Register& rd, in Bics() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 728 void Bics(const Register& rd, const Register& rn, const Operand& operand);
3588 void Bics(const PRegisterWithLaneSize& pd, in Bics() function
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 834 __ Bics(w0, w1, Operand(w1)); in TEST() local
846 __ Bics(w0, w0, Operand(w0, LSR, 1)); in TEST() local
859 __ Bics(x0, x0, Operand(x1, ROR, 1)); in TEST() local
871 __ Bics(x0, x0, 0x7fffffffffffffff); in TEST() local
883 __ Bics(w0, w0, 0xfffffff0); in TEST() local
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| D | test-assembler-sve-aarch64.cc | 1152 __ Bics(p1.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB()); in TEST_SVE() local
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1387 Bics(cond, rd, rn, operand); in Bic()
1394 Bics(cond, rd, rn, operand); in Bic()
1408 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) { in Bics() function
1418 void Bics(Register rd, Register rn, const Operand& operand) { in Bics() function
1419 Bics(al, rd, rn, operand); in Bics()
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