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Searched refs:CFGR (Results 1 – 11 of 11) sorted by relevance

/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_rcc.c300 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
316 while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) in HAL_RCC_DeInit()
459 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >>… in HAL_RCC_OscConfig()
989 ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) in HAL_RCC_ClockConfig()
991 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1032 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1039 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); in HAL_RCC_ClockConfig()
1093 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1101 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); in HAL_RCC_ClockConfig()
1124 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
[all …]
Dstm32l4xx_hal_flash_ex.c492 MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); in HAL_FLASHEx_ConfigLVEPin()
495 if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) in HAL_FLASHEx_ConfigLVEPin()
Dstm32l4xx_hal_rcc_ex.c2669 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
2701 pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_rcc.c300 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
316 while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) in HAL_RCC_DeInit()
459 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >>… in HAL_RCC_OscConfig()
989 ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) in HAL_RCC_ClockConfig()
991 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1032 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1039 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); in HAL_RCC_ClockConfig()
1093 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1101 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); in HAL_RCC_ClockConfig()
1124 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
[all …]
Dstm32l4xx_hal_flash_ex.c492 MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); in HAL_FLASHEx_ConfigLVEPin()
495 if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) in HAL_FLASHEx_ConfigLVEPin()
Dstm32l4xx_hal_rcc_ex.c2669 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
2701 pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/
Dsystem_stm32l4xx.c208 RCC->CFGR = 0x00000000U; in SystemInit()
289 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
335 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/
Dsystem_stm32l4xx.c208 RCC->CFGR = 0x00000000U; in SystemInit()
289 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
335 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rcc.h4128 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
4138 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
4166 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
4195 … MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rcc.h4128 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
4138 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
4166 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
4195 … MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
Dstm32l476xx.h199 …__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x… member
619 …__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset… member
706 …__IO uint32_t CFGR; /*!< RCC clock configuration register, … member