| /external/libxaac/decoder/ |
| D | ixheaacd_mps_nlc_dec.h | 23 #define CLD (0) macro
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| D | ixheaacd_mps_parse.c | 199 if (data_type == CLD) { in ixheaacd_mps_coarse2fine()
397 err = ixheaacd_mps_ecdata_decoding(self, bitstream, frame->cmp_cld_idx, CLD); in ixheaacd_mps_frame_parsing()
674 case CLD: in ixheaacd_mps_de_quantize()
823 if (param_type == CLD) { in ixheaacd_mps_mapindexdata()
853 cur_bit_stream_ptr->cld_idx_pre, CLD); in ixheaacd_mps_dec_and_mapframeott()
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| D | ixheaacd_mps_dec.c | 889 case CLD: in ixheaacd_huff_decode()
940 case CLD: in ixheaacd_huff_decode()
1017 case CLD: in ixheaacd_huff_decode()
1137 case CLD: in ixheaacd_huff_decode()
1281 case CLD: in ixheaacd_mps_ecdatapairdec()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 597 EmitInstruction(Out, MCInstBuilder(X86::CLD)); in EmitCallAsanReport()
866 EmitInstruction(Out, MCInstBuilder(X86::CLD)); in EmitCallAsanReport()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 744 // CLD STD.
745 def : InstRW<[WriteALU], (instrs STD, CLD)>;
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| D | X86ScheduleZnver1.td | 744 // CLD STD.
745 def : InstRW<[WriteALU], (instrs STD, CLD)>;
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| D | X86ScheduleAtom.td | 578 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
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| D | X86SchedBroadwell.td | 798 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
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| D | X86SchedSkylakeClient.td | 814 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
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| D | X86FrameLowering.cpp | 1499 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD)) in emitPrologue()
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| D | X86SchedHaswell.td | 1269 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
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| D | X86SchedSkylakeServer.td | 875 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 756 // CLD STD.
757 def : InstRW<[WriteALU], (instrs STD, CLD)>;
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| D | X86ScheduleZnver1.td | 747 // CLD STD.
748 def : InstRW<[WriteALU], (instrs STD, CLD)>;
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| D | X86ScheduleAtom.td | 581 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
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| D | X86SchedBroadwell.td | 801 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
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| D | X86SchedHaswell.td | 1272 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
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| D | X86SchedSkylakeClient.td | 817 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
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| D | X86FrameLowering.cpp | 1820 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD)) in emitPrologue()
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| D | X86SchedSkylakeServer.td | 886 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 870 // CLD STD.
874 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
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| D | X86FrameLowering.cpp | 1395 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD)) in emitPrologue()
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 413 #define CLD CHOICE(cld, cld, cld) macro
1141 #define CLD cld macro
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1_reduce.inc | 312 2965U, // CLD
2030 0U, // CLD
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 6305 {DBGFIELD("CLD") 1, false, false, 28, 1, 22, 1, 0, 0}, // #616
7682 {DBGFIELD("CLD") 1, false, false, 79, 2, 1, 1, 0, 0}, // #616
9059 {DBGFIELD("CLD") 3, false, false, 1608, 7, 22, 1, 0, 0}, // #616
10436 {DBGFIELD("CLD") 1, false, false, 1, 1, 1, 1, 0, 0}, // #616
11813 {DBGFIELD("CLD") 3, false, false, 1608, 7, 22, 1, 0, 0}, // #616
13190 {DBGFIELD("CLD") 1, false, false, 709, 2, 1, 1, 0, 0}, // #616
14567 {DBGFIELD("CLD") 3, false, false, 1608, 7, 22, 1, 0, 0}, // #616
15944 {DBGFIELD("CLD") 1, false, false, 188, 1, 1, 1, 0, 0}, // #616
17321 {DBGFIELD("CLD") 3, false, false, 1608, 7, 22, 1, 0, 0}, // #616
18698 {DBGFIELD("CLD") 1, false, false, 734, 1, 1, 1, 0, 0}, // #616
[all …]
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