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Searched refs:CPG_PLL0CR (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/renesas/rzg/
Dbl2_plat_setup.c830 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
832 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()
/external/arm-trusted-firmware/plat/renesas/common/include/
Drcar_def.h225 #define CPG_PLL0CR (CPG_BASE + 0x00D8U) macro
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl2_plat_setup.c983 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
985 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()