| /external/vixl/src/aarch64/ |
| D | registers-aarch64.cc | 35 std::string CPURegister::GetArchitecturalName() const { in GetArchitecturalName()
63 unsigned CPURegister::GetMaxCodeFor(CPURegister::RegisterBank bank) { in GetMaxCodeFor()
83 bool CPURegister::IsValidRegister() const { in IsValidRegister()
90 bool CPURegister::IsValidVRegister() const { in IsValidVRegister()
98 bool CPURegister::IsValidFPRegister() const { in IsValidFPRegister()
102 bool CPURegister::IsValidZRegister() const { in IsValidZRegister()
110 bool CPURegister::IsValidPRegister() const { in IsValidPRegister()
120 bool CPURegister::IsValid() const { in IsValid()
138 RET_TYPE CPURegister::CTOR_TYPE() const { \
173 bool AreAliased(const CPURegister& reg1, in AreAliased()
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| D | registers-aarch64.h | 73 class CPURegister {
91 VIXL_CONSTEXPR CPURegister() in CPURegister() function
98 CPURegister(int code, int size_in_bits, RegisterType type) in CPURegister() function
227 bool IsSameType(const CPURegister& other) const { in IsSameType()
231 bool IsSameBank(const CPURegister& other) const { in IsSameBank()
238 bool IsSameSizeAndType(const CPURegister& other) const { in IsSameSizeAndType()
242 bool IsSameFormat(const CPURegister& other) const { in IsSameFormat()
247 bool Aliases(const CPURegister& other) const { in Aliases()
251 bool Is(const CPURegister& other) const { in Is()
393 static unsigned GetMaxCodeFor(CPURegister::RegisterType type) { in GetMaxCodeFor()
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| D | operands-aarch64.h | 42 explicit CPURegList(CPURegister reg1,
43 CPURegister reg2 = NoCPUReg,
44 CPURegister reg3 = NoCPUReg,
45 CPURegister reg4 = NoCPUReg)
53 CPURegList(CPURegister::RegisterType type, unsigned size, RegList list) in CPURegList()
58 CPURegList(CPURegister::RegisterType type, in CPURegList()
64 ((type == CPURegister::kRegister) && (last_reg < kNumberOfRegisters)) || in CPURegList()
65 ((type == CPURegister::kVRegister) && in CPURegList()
76 static CPURegList Empty(CPURegister::RegisterType type,
77 unsigned size = CPURegister::kUnknownSize) {
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| D | operands-aarch64.cc | 33 CPURegister CPURegList::PopLowestIndex(RegList mask) { in PopLowestIndex()
39 return CPURegister(index, size_, type_); in PopLowestIndex()
43 CPURegister CPURegList::PopHighestIndex(RegList mask) { in PopHighestIndex()
50 return CPURegister(index, size_, type_); in PopHighestIndex()
55 if (type_ == CPURegister::kNoRegister) { in IsValid()
63 is_valid &= CPURegister(i, size_, type_).IsValid(); in IsValid()
72 if (GetType() == CPURegister::kRegister) { in RemoveCalleeSaved()
74 } else if (GetType() == CPURegister::kVRegister) { in RemoveCalleeSaved()
77 VIXL_ASSERT(GetType() == CPURegister::kNoRegister); in RemoveCalleeSaved()
116 return CPURegList(CPURegister::kRegister, size, 19, 29); in GetCalleeSaved()
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| D | macro-assembler-aarch64.cc | 325 p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)), in MacroAssembler()
348 p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)), in MacroAssembler()
369 p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)), in MacroAssembler()
1700 CPURegister dst_reg = dst.GetCPURegister(); in Move()
1701 CPURegister src_reg = src.GetCPURegister(); in Move()
1718 CPURegister temp = temps.AcquireCPURegisterOfSize(operand_size); in Move()
1946 void MacroAssembler::LoadStoreMacro(const CPURegister& rt, in LS_MACRO_LIST()
1994 void MacroAssembler::LoadStorePairMacro(const CPURegister& rt, in LSPAIR_MACRO_LIST()
1995 const CPURegister& rt2, in LSPAIR_MACRO_LIST()
2060 void MacroAssembler::Push(const CPURegister& src0, in Push()
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| D | macro-assembler-aarch64.h | 55 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \
56 V(Str, CPURegister&, rt, StoreOpFor(rt)) \
61 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
62 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
852 void LoadStoreMacro(const CPURegister& rt,
861 void LoadStorePairMacro(const CPURegister& rt,
862 const CPURegister& rt2,
894 void Push(const CPURegister& src0,
895 const CPURegister& src1 = NoReg,
896 const CPURegister& src2 = NoReg,
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| D | assembler-aarch64.h | 1164 void ldr(const CPURegister& rt,
1169 void str(const CPURegister& rt,
1209 void ldur(const CPURegister& rt,
1214 void stur(const CPURegister& rt,
1262 void ldp(const CPURegister& rt,
1263 const CPURegister& rt2,
1267 void stp(const CPURegister& rt,
1268 const CPURegister& rt2,
1275 void ldnp(const CPURegister& rt,
1276 const CPURegister& rt2,
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| D | assembler-aarch64.cc | 1096 void Assembler::ldp(const CPURegister& rt, in ldp()
1097 const CPURegister& rt2, in ldp()
1103 void Assembler::stp(const CPURegister& rt, in stp()
1104 const CPURegister& rt2, in stp()
1118 void Assembler::LoadStorePair(const CPURegister& rt, in LoadStorePair()
1119 const CPURegister& rt2, in LoadStorePair()
1154 void Assembler::ldnp(const CPURegister& rt, in ldnp()
1155 const CPURegister& rt2, in ldnp()
1161 void Assembler::stnp(const CPURegister& rt, in stnp()
1162 const CPURegister& rt2, in stnp()
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| D | disasm-aarch64.h | 66 const CPURegister& reg);
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| D | disasm-aarch64.cc | 9527 const CPURegister ®) { in AppendRegisterNameToOutput()
9854 CPURegister::RegisterType reg_type = CPURegister::kRegister; in SubstituteRegisterField()
9872 reg_type = CPURegister::kRegister; in SubstituteRegisterField()
9876 reg_type = CPURegister::kRegister; in SubstituteRegisterField()
9880 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
9884 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
9888 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
9892 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
9896 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
9901 reg_type = CPURegister::kVRegister; in SubstituteRegisterField()
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| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 323 VIXL_CHECK(CPURegister(0, kWRegSize, CPURegister::kRegister).Is(w0)); in TEST()
324 VIXL_CHECK(CPURegister(1, kXRegSize, CPURegister::kRegister).Is(x1)); in TEST()
326 VIXL_CHECK(CPURegister(2, kBRegSize, CPURegister::kVRegister).Is(b2)); in TEST()
327 VIXL_CHECK(CPURegister(3, kHRegSize, CPURegister::kVRegister).Is(h3)); in TEST()
328 VIXL_CHECK(CPURegister(4, kSRegSize, CPURegister::kVRegister).Is(s4)); in TEST()
329 VIXL_CHECK(CPURegister(5, kDRegSize, CPURegister::kVRegister).Is(d5)); in TEST()
330 VIXL_CHECK(CPURegister(6, kQRegSize, CPURegister::kVRegister).Is(q6)); in TEST()
331 VIXL_CHECK(CPURegister(7, kQRegSize, CPURegister::kVRegister).Is(v7)); in TEST()
333 VIXL_CHECK(CPURegister(0, CPURegister::kUnknownSize, CPURegister::kVRegister) in TEST()
335 VIXL_CHECK(CPURegister(1, CPURegister::kUnknownSize, CPURegister::kPRegister) in TEST()
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| D | test-utils-aarch64.cc | 592 if (reg_list.GetType() == CPURegister::kRegister) { in Clobber()
595 } else if (reg_list.GetType() == CPURegister::kVRegister) { in Clobber()
718 CPURegister reg = scratch_registers.PopLowestIndex(); in Dump()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 447 CPURegister reg1, in Printf()
448 CPURegister reg2, in Printf()
449 CPURegister reg3, in Printf()
450 CPURegister reg4) { in Printf()
486 if (reg1.GetType() == CPURegister::kRRegister) { in Printf()
489 if (reg2.GetType() == CPURegister::kRRegister) { in Printf()
492 if (reg3.GetType() == CPURegister::kRRegister) { in Printf()
495 if (reg4.GetType() == CPURegister::kRRegister) { in Printf()
499 VIXL_ASSERT(tmp.GetType() == CPURegister::kRRegister); in Printf()
610 void MacroAssembler::PushRegister(CPURegister reg) { in PushRegister()
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| D | instructions-aarch32.h | 59 class CPURegister {
82 CPURegister(RegisterType type, uint32_t code, int size) in CPURegister() function
128 bool IsSameFormat(CPURegister reg) { in IsSameFormat()
131 bool Is(CPURegister ref) const { return GetReg() == ref.GetReg(); } in Is()
135 class Register : public CPURegister {
137 Register() : CPURegister(kNoRegister, 0, kRegSizeInBits) {} in Register()
139 : CPURegister(kRRegister, code % kNumberOfRegisters, kRegSizeInBits) { in Register()
178 class VRegister : public CPURegister {
180 VRegister() : CPURegister(kNoRegister, 0, 0) {} in VRegister()
182 : CPURegister(type, code, size) {} in VRegister()
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| D | operands-aarch32.h | 426 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kSRegister)); in GetRegister()
468 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kDRegister)); in GetRegister()
507 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kQRegister)); in GetRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeView.h | 524 struct CPURegister { struct
525 CPURegister() = delete;
526 CPURegister(CPUType Cpu, codeview::RegisterId Reg) { in CPURegister() function
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| /external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeView.h | 524 struct CPURegister { struct
525 CPURegister() = delete;
526 CPURegister(CPUType Cpu, codeview::RegisterId Reg) { in CPURegister() function
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| /external/vixl/examples/aarch64/ |
| D | custom-disassembler.h | 49 const vixl::aarch64::CPURegister& reg) VIXL_OVERRIDE;
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| D | custom-disassembler.cc | 38 const CPURegister& reg) { in AppendRegisterNameToOutput()
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| /external/llvm-project/llvm/include/llvm/DebugInfo/PDB/ |
| D | PDBExtras.h | 30 const llvm::codeview::CPURegister &CpuReg);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/PDB/ |
| D | PDBExtras.h | 31 const llvm::codeview::CPURegister &CpuReg);
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 253 __ StoreCPURegList(CPURegList(CPURegister::kRegister, size, store_list), in GenerateMemOperandSequence()
256 __ LoadCPURegList(CPURegList(CPURegister::kRegister, size, load_list), in GenerateMemOperandSequence()
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| /external/vixl/doc/aarch64/topics/ |
| D | extending-the-disassembler.md | 17 const CPURegister& reg);
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| /external/llvm-project/llvm/tools/llvm-pdbutil/ |
| D | PrettyFunctionDumper.cpp | 141 << CPURegister{Symbol.getRawSymbol().getPlatform(), in start()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1252 void ldnp(const CPURegister& rt,
1253 const CPURegister& rt2,
1261 void ldp(const CPURegister& rt,
1262 const CPURegister& rt2,
1277 void ldr(const CPURegister& rt, RawLiteral* literal)
1284 void ldr(const CPURegister& rt, int64_t imm19)
1291 void ldr(const CPURegister& rt,
1793 void ldur(const CPURegister& rt,
2610 void stnp(const CPURegister& rt,
2611 const CPURegister& rt2,
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