| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 290 F27, F28, F29, F30, F31, CR2, CR3, CR4
298 R28, R29, R30, R31, CR2, CR3, CR4
316 F27, F28, F29, F30, F31, CR2, CR3, CR4
323 F27, F28, F29, F30, F31, CR2, CR3, CR4
332 F27, F28, F29, F30, F31, CR2, CR3, CR4
339 F27, F28, F29, F30, F31, CR2, CR3, CR4
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| D | PPCRegisterInfo.h | 42 Reg = PPC::CR4; in getCRFromCRBit()
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| D | PPCFrameLowering.cpp | 1328 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) in emitPrologue()
1334 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in emitPrologue()
1831 SavedRegs.test(PPC::CR4))) { in determineCalleeSaves()
2211 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; in spillCalleeSavedRegisters()
2303 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) in restoreCRs()
2395 } else if (Reg == PPC::CR4) { in restoreCalleeSavedRegisters()
2402 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in restoreCalleeSavedRegisters()
|
| D | PPCRegisterInfo.td | 211 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
369 CR7, CR2, CR3, CR4)>;
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_hal_pwr_ex.c | 304 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); in HAL_PWREx_EnableBatteryCharging()
307 SET_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_EnableBatteryCharging()
317 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_DisableBatteryCharging()
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| D | stm32l4xx_hal_pwr.c | 414 …MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SH… in HAL_PWR_EnableWakeUpPin()
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_hal_pwr_ex.c | 304 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); in HAL_PWREx_EnableBatteryCharging()
307 SET_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_EnableBatteryCharging()
317 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_DisableBatteryCharging()
|
| D | stm32l4xx_hal_pwr.c | 414 …MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SH… in HAL_PWR_EnableWakeUpPin()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 226 F27, F28, F29, F30, F31, CR2, CR3, CR4
235 F27, F28, F29, F30, F31, CR2, CR3, CR4
244 F27, F28, F29, F30, F31, CR2, CR3, CR4
253 F27, F28, F29, F30, F31, CR2, CR3, CR4
|
| D | PPCRegisterInfo.h | 42 Reg = PPC::CR4; in getCRFromCRBit()
|
| D | PPCFrameLowering.cpp | 1069 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) in emitPrologue()
1075 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in emitPrologue()
1435 SavedRegs.test(PPC::CR4))) { in determineCalleeSaves()
1738 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; in spillCalleeSavedRegisters()
1810 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) in restoreCRs()
1899 } else if (Reg == PPC::CR4) { in restoreCalleeSavedRegisters()
1906 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in restoreCalleeSavedRegisters()
|
| D | PPCRegisterInfo.td | 198 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
345 CR7, CR2, CR3, CR4)>;
|
| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …GS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9…
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenRegisterInfo.inc | 36 CR4 = 16,
1396 PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
1816 { 72U, PPC::CR4 },
1961 { 72U, PPC::CR4 },
2104 { 72U, PPC::CR4 },
2249 { 72U, PPC::CR4 },
2333 { PPC::CR4, 72U },
2608 { PPC::CR4, 72U },
2886 { PPC::CR4, 72U },
3161 { PPC::CR4, 72U },
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 34 #pragma push_macro("CR4")
97 CV_REGISTER(CR4, 84)
365 #pragma pop_macro("CR4")
|
| /external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 35 #pragma push_macro("CR4")
98 CV_REGISTER(CR4, 84)
366 #pragma pop_macro("CR4")
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 42 Reg = PPC::CR4; in getCRFromCRBit()
|
| D | PPCCallingConv.td | 273 R28, R29, R30, R31, CR2, CR3, CR4
291 F27, F28, F29, F30, F31, CR2, CR3, CR4
301 F27, F28, F29, F30, F31, CR2, CR3, CR4
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| D | PPCFrameLowering.cpp | 1145 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) in emitPrologue()
1151 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { in emitPrologue()
1953 SavedRegs.test(PPC::CR4))) { in determineCalleeSaves()
2290 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; in spillCalleeSavedRegisters()
2382 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) in restoreCRs()
2426 return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4; in isCalleeSavedCR()
2469 } else if (Reg == PPC::CR4) { in restoreCalleeSavedRegisters()
|
| D | PPCRegisterInfo.td | 240 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
395 CR7, CR2, CR3, CR4)> {
396 let AltOrders = [(sub CRRC, CR2, CR3, CR4)];
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.h | 187 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7}
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 365 case PPC::CR4: RegNo = 4; break; in printcrbitm()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 367 ENTRY(CR4) \
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 359 ENTRY(CR4) \
|
| /external/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 364 ENTRY(CR4) \
|