1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_cadence 1 14 #define ZYNQMP_CONSOLE_ID_cadence0 1 15 #define ZYNQMP_CONSOLE_ID_cadence1 2 16 #define ZYNQMP_CONSOLE_ID_dcc 3 17 18 #define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 19 20 /* Firmware Image Package */ 21 #define ZYNQMP_PRIMARY_CPU 0 22 23 /* Memory location options for Shared data and TSP in ZYNQMP */ 24 #define ZYNQMP_IN_TRUSTED_SRAM 0 25 #define ZYNQMP_IN_TRUSTED_DRAM 1 26 27 /******************************************************************************* 28 * ZYNQMP memory map related constants 29 ******************************************************************************/ 30 /* Aggregate of all devices in the first GB */ 31 #define DEVICE0_BASE U(0xFF000000) 32 #define DEVICE0_SIZE U(0x00E00000) 33 #define DEVICE1_BASE U(0xF9000000) 34 #define DEVICE1_SIZE U(0x00800000) 35 36 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 37 #define CRF_APB_BASE U(0xFD1A0000) 38 #define CRF_APB_SIZE U(0x00600000) 39 #define CRF_APB_CLK_BASE U(0xFD1A0020) 40 41 /* CRF registers and bitfields */ 42 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 43 44 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 45 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 46 47 /* CRL registers and bitfields */ 48 #define CRL_APB_BASE U(0xFF5E0000) 49 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 50 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 51 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 52 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 53 #define CRL_APB_CLK_BASE U(0xFF5E0020) 54 55 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 56 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 57 58 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 59 60 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 61 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 62 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 63 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 64 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 65 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 66 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 67 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 68 #define ZYNQMP_BOOTMODE_JTAG U(0) 69 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 70 CRL_APB_BOOT_DRIVE_PIN_1) 71 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 72 73 /* system counter registers and bitfields */ 74 #define IOU_SCNTRS_BASE 0xFF260000 75 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 76 77 /* APU registers and bitfields */ 78 #define APU_BASE 0xFD5C0000 79 #define APU_CONFIG_0 (APU_BASE + 0x20) 80 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 81 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 82 #define APU_PWRCTL (APU_BASE + 0x90) 83 84 #define APU_CONFIG_0_VINITHI_SHIFT 8 85 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 86 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 87 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 88 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 89 90 /* PMU registers and bitfields */ 91 #define PMU_GLOBAL_BASE 0xFFD80000 92 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 93 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 94 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 95 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 96 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 97 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 98 99 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 100 101 /******************************************************************************* 102 * CCI-400 related constants 103 ******************************************************************************/ 104 #define PLAT_ARM_CCI_BASE 0xFD6E0000 105 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 106 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 107 108 /******************************************************************************* 109 * GIC-400 & interrupt handling related constants 110 ******************************************************************************/ 111 #define BASE_GICD_BASE 0xF9010000 112 #define BASE_GICC_BASE 0xF9020000 113 #define BASE_GICH_BASE 0xF9040000 114 #define BASE_GICV_BASE 0xF9060000 115 116 #if ZYNQMP_WDT_RESTART 117 #define IRQ_SEC_IPI_APU 67 118 #define IRQ_TTC3_1 77 119 #define TTC3_BASE_ADDR 0xFF140000 120 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 121 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 122 #endif 123 124 #define ARM_IRQ_SEC_PHY_TIMER 29 125 126 #define ARM_IRQ_SEC_SGI_0 8 127 #define ARM_IRQ_SEC_SGI_1 9 128 #define ARM_IRQ_SEC_SGI_2 10 129 #define ARM_IRQ_SEC_SGI_3 11 130 #define ARM_IRQ_SEC_SGI_4 12 131 #define ARM_IRQ_SEC_SGI_5 13 132 #define ARM_IRQ_SEC_SGI_6 14 133 #define ARM_IRQ_SEC_SGI_7 15 134 135 #define MAX_INTR_EL3 128 136 137 /******************************************************************************* 138 * UART related constants 139 ******************************************************************************/ 140 #define ZYNQMP_UART0_BASE 0xFF000000 141 #define ZYNQMP_UART1_BASE 0xFF010000 142 143 #if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc) 144 # define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE 145 #elif ZYNQMP_CONSOLE_IS(cadence1) 146 # define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE 147 #else 148 # error "invalid ZYNQMP_CONSOLE" 149 #endif 150 151 #define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE 152 /* impossible to call C routine how it is done now - hardcode any value */ 153 #define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */ 154 /* Must be non zero */ 155 #define ZYNQMP_UART_BAUDRATE 115200 156 157 /* Silicon version detection */ 158 #define ZYNQMP_SILICON_VER_MASK 0xF000 159 #define ZYNQMP_SILICON_VER_SHIFT 12 160 #define ZYNQMP_CSU_VERSION_SILICON 0 161 #define ZYNQMP_CSU_VERSION_QEMU 3 162 163 #define ZYNQMP_RTL_VER_MASK 0xFF0 164 #define ZYNQMP_RTL_VER_SHIFT 4 165 166 #define ZYNQMP_PS_VER_MASK 0xF 167 #define ZYNQMP_PS_VER_SHIFT 0 168 169 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 170 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40 171 172 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0 173 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << \ 174 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 175 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 176 177 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 178 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << \ 179 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 180 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 181 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << \ 182 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 183 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19 184 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << \ 185 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 186 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21 187 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << \ 188 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 189 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 190 191 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28 192 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << \ 193 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 194 #define ZYNQMP_CSU_IDCODE_REVISION 0 195 196 #define ZYNQMP_CSU_VERSION_OFFSET 0x44 197 198 /* Efuse */ 199 #define EFUSE_BASEADDR 0xFFCC0000 200 #define EFUSE_IPDISABLE_OFFSET 0x1018 201 #define EFUSE_IPDISABLE_VERSION 0x1FFU 202 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 203 204 /* Access control register defines */ 205 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 206 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 207 208 #define FPD_SLCR_BASEADDR U(0xFD610000) 209 #define IOU_SLCR_BASEADDR U(0xFF180000) 210 211 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 212 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 213 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 214 #define ZYNQMP_SLSPLIT_MASK U(0x08) 215 #define ZYNQMP_TCM_COMB_MASK U(0x40) 216 #define ZYNQMP_SLCLAMP_MASK U(0x10) 217 #define ZYNQMP_VINITHI_MASK U(0x04) 218 219 /* Tap delay bypass */ 220 #define IOU_TAPDLY_BYPASS U(0XFF180390) 221 #define TAP_DELAY_MASK U(0x7) 222 223 /* SGMII mode */ 224 #define IOU_GEM_CTRL U(0xFF180360) 225 #define IOU_GEM_CLK_CTRL U(0xFF180308) 226 #define SGMII_SD_MASK U(0x3) 227 #define SGMII_SD_OFFSET U(2) 228 #define SGMII_PCS_SD_0 U(0x0) 229 #define SGMII_PCS_SD_1 U(0x1) 230 #define SGMII_PCS_SD_PHY U(0x2) 231 #define GEM_SGMII_MASK U(0x4) 232 #define GEM_CLK_CTRL_MASK U(0xF) 233 #define GEM_CLK_CTRL_OFFSET U(5) 234 #define GEM_RX_SRC_SEL_GTR U(0x1) 235 #define GEM_SGMII_MODE U(0x4) 236 237 /* SD DLL reset */ 238 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 239 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 240 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 241 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 242 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 243 244 /* SD tap delay */ 245 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 246 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 247 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 248 #define ZYNQMP_SD_TAP_OFFSET U(16) 249 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 250 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 251 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 252 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 253 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 254 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 255 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 256 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 257 258 /* Clock control registers */ 259 /* Full power domain clocks */ 260 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 261 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 262 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 263 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 264 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 265 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 266 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 267 /* Peripheral clocks */ 268 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 269 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 270 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 271 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 272 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 273 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 274 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 275 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 276 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 277 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 278 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 279 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 280 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 281 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 282 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 283 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 284 285 /* Low power domain clocks */ 286 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 287 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 288 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 289 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 290 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 291 /* Peripheral clocks */ 292 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 293 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 294 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 295 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 296 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 297 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 298 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 299 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 300 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 301 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 302 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 303 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 304 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 305 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 306 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 307 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 308 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 309 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 310 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 311 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 312 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 313 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 314 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 315 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 316 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 317 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 318 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 319 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 320 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 321 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 322 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 323 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 324 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 325 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 326 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 327 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 328 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 329 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 330 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 331 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 332 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 333 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 334 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 335 336 /* Global general storage register base address */ 337 #define GGS_BASEADDR (0xFFD80030U) 338 #define GGS_NUM_REGS U(4) 339 340 /* Persistent global general storage register base address */ 341 #define PGGS_BASEADDR (0xFFD80050U) 342 #define PGGS_NUM_REGS U(4) 343 344 /* PMU GGS4 register 4 is used for warm restart boot health status */ 345 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 346 /* Warm restart boot health status mask */ 347 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 348 /* WDT restart scope shift and mask */ 349 #define RESTART_SCOPE_SHIFT (3) 350 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 351 352 /*AFI registers */ 353 #define AFIFM6_WRCTRL U(13) 354 #define FABRIC_WIDTH U(3) 355 356 /* CSUDMA Module Base Address*/ 357 #define CSUDMA_BASE 0xFFC80000 358 359 /* RSA-CORE Module Base Address*/ 360 #define RSA_CORE_BASE 0xFFCE0000 361 362 #endif /* ZYNQMP_DEF_H */ 363