Searched refs:CRRegs (Results 1 – 11 of 11) sorted by relevance
| /external/capstone/arch/PowerPC/ |
| D | PPCDisassembler.c | 38 static const unsigned CRRegs[] = { variable
178 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
347 MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); in decodeCRBitMOperand()
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 65 static const unsigned CRRegs[] = { variable
218 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
224 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRC0RegisterClass()
393 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | circ_ldd_bug.ll | 10 ; %0 (CRRegs) = TFCR %0 (IntRegs)
12 ; %1 (CRRegs) = TFCR %1 (IntRegs)
14 ; The scheduler would move the CRRegs to the top of the loop. The allocator
15 ; would try to spill the CRRegs after running out of them. We don't have code to
16 ; spill CRRegs and the above assertion would be triggered.
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | circ_ldd_bug.ll | 10 ; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs)
12 ; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs)
14 ; The scheduler would move the CRRegs to the top of the loop. The allocator
15 ; would try to spill the CRRegs after running out of them. We don't have code to
16 ; spill CRRegs and the above assertion would be triggered.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 85 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
317 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 92 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
376 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.h | 187 static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.h | 185 static const MCPhysReg CRRegs[8] = { \
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 173 static const MCPhysReg CRRegs[8] = { variable
641 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
646 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
1305 RegNo = CRRegs[IntVal]; in MatchRegisterName()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 538 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
543 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
1235 RegNo = CRRegs[IntVal]; in MatchRegisterName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 514 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); in addRegCRRCOperands()
519 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); in addCRBitMaskOperands()
1202 RegNo = CRRegs[IntVal]; in MatchRegisterName()
|