| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | select-select.mir | 104 ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
160 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
218 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
247 ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc
276 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
303 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
330 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
605 ; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
634 ; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc
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| D | fold-brcond-fcmp.mir | 4 # Test that we don't have to emit a CSINC when emitting a G_FCMP being used by
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | cond-sel-value-prop.ll | 50 ; CSINC to materialize the 1.
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| D | arm64-early-ifcvt.ll | 396 ; This function from 175.vpr folds an ADDWri into a CSINC.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 47 CSINC, // Conditional select increment. enumerator
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| D | AArch64SchedCyclone.td | 145 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedKryoDetails.td | 550 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 85 #define CSINC 0x9a800400 macro
1806 FAIL_IF(push_inst(compiler, CSINC | (cc << 12) | RD(dst_r) | RN(TMP_ZERO) | RM(TMP_ZERO))); in sljit_emit_op_flags()
1831 FAIL_IF(push_inst(compiler, CSINC | (cc << 12) | RD(TMP_REG2) | RN(TMP_ZERO) | RM(TMP_ZERO))); in sljit_emit_op_flags()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-early-ifcvt.ll | 396 ; This function from 175.vpr folds an ADDWri into a CSINC.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 255 CSINC, // Conditional select increment. enumerator
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| D | ARMISelLowering.cpp | 1707 case ARMISD::CSINC: return "ARMISD::CSINC"; in getTargetNodeName()
4972 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
4974 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
4983 if (Opcode != ARMISD::CSINC && in LowerSELECT_CC()
4993 if (FVal == 0 && Opcode != ARMISD::CSINC) { in LowerSELECT_CC()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 47 CSINC, // Conditional select increment. enumerator
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| D | AArch64SchedThunderX2T99.td | 432 "CSINC(W|X)r", "CSINV(W|X)r",
454 "CSINC(W|X)r", "CSINV(W|X)r",
473 "CSINC(W|X)r", "CSINV(W|X)r",
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| D | AArch64SchedCyclone.td | 146 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| D | AArch64SchedKryoDetails.td | 549 (instregex "(CSINC|CSNEG)(W|X)r")>;
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 298 CSINC, // Conditional select increment. enumerator
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 67 CSINC, // Conditional select increment. enumerator
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| D | AArch64SchedThunderX3T110.td | 692 "CSINC(W|X)r", "CSINV(W|X)r",
714 "CSINC(W|X)r", "CSINV(W|X)r",
733 "CSINC(W|X)r", "CSINV(W|X)r",
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| D | AArch64SchedThunderX2T99.td | 432 "CSINC(W|X)r", "CSINV(W|X)r",
454 "CSINC(W|X)r", "CSINV(W|X)r",
473 "CSINC(W|X)r", "CSINV(W|X)r",
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| D | AArch64SchedCyclone.td | 147 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedTSV110.td | 376 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| D | AArch64SchedKryoDetails.td | 549 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1396 CSINC = CSINC_w, enumerator
|