| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 125 for (unsigned Chan = 0; Chan < 4; ++Chan) { in runOnMachineFunction() local
128 if (Chan < 2) in runOnMachineFunction()
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; in runOnMachineFunction()
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
136 if (Chan > 0) { in runOnMachineFunction()
139 if (Chan >= 2) in runOnMachineFunction()
141 if (Chan != 3) in runOnMachineFunction()
154 for (unsigned Chan = 0; Chan < 4; ++Chan) { in runOnMachineFunction() local
157 if (Chan < 2) in runOnMachineFunction()
[all …]
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| D | R600RegisterInfo.td | 45 foreach Chan = [ "X", "Y", "Z", "W" ] in {
47 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
50 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
51 Index, Chan>;
67 foreach Chan = [ "X", "Y", "Z", "W"] in {
69 let chan_encoding = !if(!eq(Chan, "X"), 0,
70 !if(!eq(Chan, "Y"), 1,
71 !if(!eq(Chan, "Z"), 2,
72 !if(!eq(Chan, "W"), 3, 0)))) in {
73 def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
[all …]
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| D | R600OptimizeVectorRegisters.cpp | 72 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() local
74 UndefReg.push_back(Chan); in RegSeqInfo()
76 RegToChan[MO.getReg()] = Chan; in RegSeqInfo()
171 unsigned Chan) { in getReassignedChan() argument
173 if (RemapChan[j].first == Chan) in getReassignedChan()
195 unsigned Chan = getReassignedChan(RemapChan, Swizzle); in RebuildVector() local
201 .addImm(Chan); in RebuildVector()
202 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
204 std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan); in RebuildVector()
207 assert(std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan) == in RebuildVector()
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| D | R600MachineScheduler.cpp | 439 for (int Chan = 3; Chan > -1; --Chan) { in pickAlu() local
440 bool isOccupied = OccupedSlotsMask & (1 << Chan); in pickAlu()
442 SUnit *SU = AttemptFillSlot(Chan, false); in pickAlu()
444 OccupedSlotsMask |= (1 << Chan); in pickAlu()
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| D | R600EmitClauseMarkers.cpp | 135 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31; in SubstituteKCacheBank() local
136 unsigned KCacheIndex = Index * 4 + Chan; in SubstituteKCacheBank()
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| D | R600InstrInfo.cpp | 373 unsigned Chan = RI.getHWRegChan(Reg); in ExtractSrcs() local
374 Result.push_back(std::make_pair(Index, Chan)); in ExtractSrcs()
639 unsigned Chan = RI.getHWRegChan(Src.first->getReg()); in fitsConstReadLimitations() local
640 Consts.push_back((Index << 2) | Chan); in fitsConstReadLimitations()
1122 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { in reserveIndirectRegisters() local
1123 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600RegisterInfo.td | 45 foreach Chan = [ "X", "Y", "Z", "W" ] in {
47 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
50 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
51 Index, Chan>;
67 foreach Chan = [ "X", "Y", "Z", "W"] in {
69 let chan_encoding = !if(!eq(Chan, "X"), 0,
70 !if(!eq(Chan, "Y"), 1,
71 !if(!eq(Chan, "Z"), 2,
72 !if(!eq(Chan, "W"), 3, 0)))) in {
73 def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
[all …]
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| D | R600ExpandSpecialInstrs.cpp | 141 for (unsigned Chan = 0; Chan < 4; ++Chan) { in runOnMachineFunction() local
142 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
144 R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
146 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg); in runOnMachineFunction()
147 if (Chan > 0) { in runOnMachineFunction()
153 if (Chan != 3) in runOnMachineFunction()
207 for (unsigned Chan = 0; Chan < 4; Chan++) { in runOnMachineFunction() local
222 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
227 unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
228 unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
[all …]
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| D | R600OptimizeVectorRegisters.cpp | 79 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() local
81 UndefReg.push_back(Chan); in RegSeqInfo()
83 RegToChan[MO.getReg()] = Chan; in RegSeqInfo()
189 unsigned Chan) { in getReassignedChan() argument
191 if (RemapChan[j].first == Chan) in getReassignedChan()
213 unsigned Chan = getReassignedChan(RemapChan, Swizzle); in RebuildVector() local
219 .addImm(Chan); in RebuildVector()
220 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
221 std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); in RebuildVector()
224 assert(!is_contained(UpdatedUndef, Chan) && in RebuildVector()
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| D | R600MachineScheduler.cpp | 437 for (int Chan = 3; Chan > -1; --Chan) { in pickAlu() local
438 bool isOccupied = OccupedSlotsMask & (1 << Chan); in pickAlu()
440 SUnit *SU = AttemptFillSlot(Chan, false); in pickAlu()
442 OccupedSlotsMask |= (1 << Chan); in pickAlu()
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| D | R600EmitClauseMarkers.cpp | 146 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31; in SubstituteKCacheBank() local
147 unsigned KCacheIndex = Index * 4 + Chan; in SubstituteKCacheBank()
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| D | R600InstrInfo.cpp | 365 unsigned Chan = RI.getHWRegChan(Reg); in ExtractSrcs() local
366 Result.push_back(std::make_pair(Index, Chan)); in ExtractSrcs()
627 unsigned Chan = RI.getHWRegChan(Src.first->getReg()); in fitsConstReadLimitations() local
628 Consts.push_back((Index << 2) | Chan); in fitsConstReadLimitations()
1102 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { in reserveIndirectRegisters() local
1103 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600RegisterInfo.td | 45 foreach Chan = [ "X", "Y", "Z", "W" ] in {
47 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
50 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
51 Index, Chan>;
67 foreach Chan = [ "X", "Y", "Z", "W"] in {
69 let chan_encoding = !if(!eq(Chan, "X"), 0,
70 !if(!eq(Chan, "Y"), 1,
71 !if(!eq(Chan, "Z"), 2,
72 !if(!eq(Chan, "W"), 3, 0)))) in {
73 def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
[all …]
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| D | R600ExpandSpecialInstrs.cpp | 141 for (unsigned Chan = 0; Chan < 4; ++Chan) { in runOnMachineFunction() local
142 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
144 R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
146 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg); in runOnMachineFunction()
147 if (Chan > 0) { in runOnMachineFunction()
153 if (Chan != 3) in runOnMachineFunction()
207 for (unsigned Chan = 0; Chan < 4; Chan++) { in runOnMachineFunction() local
222 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
227 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
228 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
[all …]
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| D | R600OptimizeVectorRegisters.cpp | 78 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() local
80 UndefReg.push_back(Chan); in RegSeqInfo()
82 RegToChan[MO.getReg()] = Chan; in RegSeqInfo()
193 unsigned Chan) { in getReassignedChan() argument
195 if (RemapChan[j].first == Chan) in getReassignedChan()
217 unsigned Chan = getReassignedChan(RemapChan, Swizzle); in RebuildVector() local
223 .addImm(Chan); in RebuildVector()
224 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
225 std::vector<Register>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); in RebuildVector()
228 assert(!is_contained(UpdatedUndef, Chan) && in RebuildVector()
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| D | R600MachineScheduler.cpp | 437 for (int Chan = 3; Chan > -1; --Chan) { in pickAlu() local
438 bool isOccupied = OccupedSlotsMask & (1 << Chan); in pickAlu()
440 SUnit *SU = AttemptFillSlot(Chan, false); in pickAlu()
442 OccupedSlotsMask |= (1 << Chan); in pickAlu()
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| D | R600EmitClauseMarkers.cpp | 146 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31; in SubstituteKCacheBank() local
147 unsigned KCacheIndex = Index * 4 + Chan; in SubstituteKCacheBank()
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| D | R600InstrInfo.cpp | 365 unsigned Chan = RI.getHWRegChan(Reg); in ExtractSrcs() local
366 Result.push_back(std::make_pair(Index, Chan)); in ExtractSrcs()
627 unsigned Chan = RI.getHWRegChan(Src.first->getReg()); in fitsConstReadLimitations() local
628 Consts.push_back((Index << 2) | Chan); in fitsConstReadLimitations()
1103 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { in reserveIndirectRegisters() local
1104 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
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| /external/rust/crates/crossbeam-channel/tests/ |
| D | golang.rs | 27 struct Chan<T> { struct
36 impl<T> Clone for Chan<T> { implementation
37 fn clone(&self) -> Chan<T> { in clone()
38 Chan { in clone()
44 impl<T> Chan<T> { implementation
92 impl<T> Iterator for Chan<T> { implementation
100 impl<'a, T> IntoIterator for &'a Chan<T> { implementation
102 type IntoIter = Chan<T>;
109 fn make<T>(cap: usize) -> Chan<T> { in make()
111 Chan { in make()
[all …]
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| /external/swiftshader/src/System/ |
| D | Synchronization.hpp | 109 class Chan class
112 Chan();
139 Chan<T>::Chan() in Chan() function in sw::Chan
143 T Chan<T>::take() in take()
154 std::pair<T, bool> Chan<T>::tryTake() in tryTake()
167 void Chan<T>::put(const T &item) in put()
175 size_t Chan<T>::count() in count()
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| /external/rust/crates/tokio/src/sync/mpsc/ |
| D | chan.rs | 16 inner: Arc<Chan<T, S>>,
27 inner: Arc<Chan<T, S>>,
46 struct Chan<T, S> { struct
68 impl<T, S> fmt::Debug for Chan<T, S> implementation
101 unsafe impl<T: Send, S: Send> Send for Chan<T, S> {} implementation
102 unsafe impl<T: Send, S: Sync> Sync for Chan<T, S> {} implementation
107 let chan = Arc::new(Chan { in channel()
125 fn new(chan: Arc<Chan<T, S>>) -> Tx<T, S> { in new()
196 fn new(chan: Arc<Chan<T, S>>) -> Rx<T, S> { in new()
286 impl<T, S> Chan<T, S> { implementation
[all …]
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| /external/rust/crates/tokio/src/sync/tests/ |
| D | loom_atomic_waker.rs | 11 struct Chan { struct
21 let chan = Arc::new(Chan { in basic_notification() argument
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| /external/swiftshader/src/Vulkan/ |
| D | VkQueue.hpp | 84 sw::Chan<Task> pending;
85 sw::Chan<VkSubmitInfo *> toDelete;
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| /external/OpenCSD/decoder/docs/ |
| D | test_progs.md | 130 Idx:22; ID:20; C8:Set current channel.; Chan=0x0001
132 Idx:28; ID:20; C8:Set current channel.; Chan=0x0002
135 Idx:36; ID:20; C8:Set current channel.; Chan=0x0003
137 Idx:42; ID:20; C8:Set current channel.; Chan=0x0004
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| /external/icu/icu4c/source/data/curr/ |
| D | vai_Latn.txt | 45 "Chaníĩ Yuwaŋ Rɛŋmimbi",
|