/external/grpc-grpc/src/csharp/Grpc.IntegrationTesting/ |
D | WorkerServiceImpl.cs | 52 Cores = Environment.ProcessorCount, in RunServer() 90 return Task.FromResult(new CoreResponse { Cores = Environment.ProcessorCount }); in CoreCount()
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D | Control.cs | 2804 public int Cores { property in Grpc.Testing.ServerStatus 2826 if (Cores != other.Cores) return false; in Equals() 2835 if (Cores != 0) hash ^= Cores.GetHashCode(); in GetHashCode() 2857 if (Cores != 0) { in WriteTo() 2859 output.WriteInt32(Cores); in WriteTo() 2875 if (Cores != 0) { in CalculateSize() 2876 size += 1 + pb::CodedOutputStream.ComputeInt32Size(Cores); in CalculateSize() 2898 if (other.Cores != 0) { in MergeFrom() 2899 Cores = other.Cores; in MergeFrom() 2924 Cores = input.ReadInt32(); in MergeFrom() [all …]
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/external/tensorflow/tensorflow/stream_executor/tpu/ |
D | tpu_topology.h | 54 std::vector<TpuCoreLocationExternal> Cores(TpuCoreTypeEnum core_type) const;
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D | tpu_topology.cc | 49 std::vector<TpuCoreLocationExternal> TpuHostLocationExternal::Cores( in Cores() function in tensorflow::tpu::TpuHostLocationExternal
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/external/llvm/test/CodeGen/X86/ |
D | stack-update-frame-opcode.ll | 12 ; Cores use sub/add to update the SP. Opcode bitness depends on data model.
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/external/llvm-project/llvm/test/CodeGen/X86/ |
D | stack-update-frame-opcode.ll | 12 ; Cores use sub/add to update the SP. Opcode bitness depends on data model.
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/external/cpuinfo/ |
D | README.md | 26 - Cores and logical processors (hyper-threads) sharing the cache 122 - [x] Cores
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/external/llvm-project/llvm/lib/Support/Windows/ |
D | Threading.inc | 225 static unsigned Cores = 229 return Cores;
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/external/tensorflow/tensorflow/compiler/xla/pjrt/ |
D | tpu_client.cc | 105 int num_local_devices = host.Cores(kTensorCore).size(); in GetDefaultDeviceAssignment()
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/external/grpc-grpc/test/cpp/qps/ |
D | driver.cc | 113 static int Cores(int n) { return n; } in Cores() function 122 auto qps_per_server_core = qps / sum(result->server_cores(), Cores); in postprocess_scenario_result()
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/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/ |
D | layout_optimization_layout_assignment_gpu_cc_60.mlir | 10 // compute capability 7.0 (NVIDIA Tensor Cores).
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D | layout_optimization_to_nhwc.mlir | 16 // To be able to use Tensor Cores on latest NVIDIA GPUs this model has to be
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D | layout_optimization_layout_assignment_gpu_cc_70.mlir | 52 // To use Tensor Cores for f16 data type, input must be in NHWC data format.
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/external/pigweed/targets/arduino/ |
D | target_docs.rst | 48 Installing Arduino Cores
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/external/libexif/po/ |
D | pt_BR.po | 3577 msgstr "Espaço de Cores" 5263 msgstr "Cores"
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/external/tensorflow/ |
D | RELEASE.md | 1786 `float16` for acceleration on Volta and Turing Tensor Cores. This feature
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/external/cpuinfo/test/dmesg/ |
D | huawei-mate-8.log | 6597 [ 14.103302s][pid:1182,cpu4,NPDecoder]imgvideo:core: [Device Configuration] APM:n, Cores:1, Slots…
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/external/strace/ |
D | ChangeLog | 44644 Add support for ARC Cores from Synopsys.
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