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Searched refs:Cores (Results 1 – 18 of 18) sorted by relevance

/external/grpc-grpc/src/csharp/Grpc.IntegrationTesting/
DWorkerServiceImpl.cs52 Cores = Environment.ProcessorCount, in RunServer()
90 return Task.FromResult(new CoreResponse { Cores = Environment.ProcessorCount }); in CoreCount()
DControl.cs2804 public int Cores { property in Grpc.Testing.ServerStatus
2826 if (Cores != other.Cores) return false; in Equals()
2835 if (Cores != 0) hash ^= Cores.GetHashCode(); in GetHashCode()
2857 if (Cores != 0) { in WriteTo()
2859 output.WriteInt32(Cores); in WriteTo()
2875 if (Cores != 0) { in CalculateSize()
2876 size += 1 + pb::CodedOutputStream.ComputeInt32Size(Cores); in CalculateSize()
2898 if (other.Cores != 0) { in MergeFrom()
2899 Cores = other.Cores; in MergeFrom()
2924 Cores = input.ReadInt32(); in MergeFrom()
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/external/tensorflow/tensorflow/stream_executor/tpu/
Dtpu_topology.h54 std::vector<TpuCoreLocationExternal> Cores(TpuCoreTypeEnum core_type) const;
Dtpu_topology.cc49 std::vector<TpuCoreLocationExternal> TpuHostLocationExternal::Cores( in Cores() function in tensorflow::tpu::TpuHostLocationExternal
/external/llvm/test/CodeGen/X86/
Dstack-update-frame-opcode.ll12 ; Cores use sub/add to update the SP. Opcode bitness depends on data model.
/external/llvm-project/llvm/test/CodeGen/X86/
Dstack-update-frame-opcode.ll12 ; Cores use sub/add to update the SP. Opcode bitness depends on data model.
/external/cpuinfo/
DREADME.md26 - Cores and logical processors (hyper-threads) sharing the cache
122 - [x] Cores
/external/llvm-project/llvm/lib/Support/Windows/
DThreading.inc225 static unsigned Cores =
229 return Cores;
/external/tensorflow/tensorflow/compiler/xla/pjrt/
Dtpu_client.cc105 int num_local_devices = host.Cores(kTensorCore).size(); in GetDefaultDeviceAssignment()
/external/grpc-grpc/test/cpp/qps/
Ddriver.cc113 static int Cores(int n) { return n; } in Cores() function
122 auto qps_per_server_core = qps / sum(result->server_cores(), Cores); in postprocess_scenario_result()
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dlayout_optimization_layout_assignment_gpu_cc_60.mlir10 // compute capability 7.0 (NVIDIA Tensor Cores).
Dlayout_optimization_to_nhwc.mlir16 // To be able to use Tensor Cores on latest NVIDIA GPUs this model has to be
Dlayout_optimization_layout_assignment_gpu_cc_70.mlir52 // To use Tensor Cores for f16 data type, input must be in NHWC data format.
/external/pigweed/targets/arduino/
Dtarget_docs.rst48 Installing Arduino Cores
/external/libexif/po/
Dpt_BR.po3577 msgstr "Espaço de Cores"
5263 msgstr "Cores"
/external/tensorflow/
DRELEASE.md1786 `float16` for acceleration on Volta and Turing Tensor Cores. This feature
/external/cpuinfo/test/dmesg/
Dhuawei-mate-8.log6597 [ 14.103302s][pid:1182,cpu4,NPDecoder]imgvideo:core: [Device Configuration] APM:n, Cores:1, Slots…
/external/strace/
DChangeLog44644 Add support for ARC Cores from Synopsys.